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author | Marcin Bukat <marcin.bukat@gmail.com> | 2012-12-04 09:15:50 +0100 |
---|---|---|
committer | Marcin Bukat <marcin.bukat@gmail.com> | 2012-12-04 09:18:12 +0100 |
commit | e1ea08417bca57c607df6686472fa0a86f38b6d1 (patch) | |
tree | a30a9676c4262ecd83aa3fe28f9159852184c6da /firmware/target/arm | |
parent | f551d14bdd1f6160b06e739334b5e0150e645f10 (diff) | |
download | rockbox-e1ea08417bca57c607df6686472fa0a86f38b6d1.tar.gz rockbox-e1ea08417bca57c607df6686472fa0a86f38b6d1.zip |
rk27xx: introduce meaningfull constants in usb driver
Based on pamaury's work. No (un)functional change yet.
Change-Id: I7fe76c1da20d87d6c92eb3792e3d352877d423d7
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/rk27xx/usb-drv-rk27xx.c | 156 |
1 files changed, 78 insertions, 78 deletions
diff --git a/firmware/target/arm/rk27xx/usb-drv-rk27xx.c b/firmware/target/arm/rk27xx/usb-drv-rk27xx.c index 3001509069..401df17133 100644 --- a/firmware/target/arm/rk27xx/usb-drv-rk27xx.c +++ b/firmware/target/arm/rk27xx/usb-drv-rk27xx.c | |||
@@ -120,16 +120,16 @@ static void ctr_write(void) | |||
120 | int xfer_size = (ctrlep[DIR_IN].cnt > 64) ? 64 : ctrlep[DIR_IN].cnt; | 120 | int xfer_size = (ctrlep[DIR_IN].cnt > 64) ? 64 : ctrlep[DIR_IN].cnt; |
121 | unsigned int timeout = current_tick + HZ/10; | 121 | unsigned int timeout = current_tick + HZ/10; |
122 | 122 | ||
123 | while (TX0BUF & (1<<0)) /* TX0FULL flag */ | 123 | while (TX0BUF & TXFULL) /* TX0FULL flag */ |
124 | { | 124 | { |
125 | if(TIME_AFTER(current_tick, timeout)) | 125 | if(TIME_AFTER(current_tick, timeout)) |
126 | break; | 126 | break; |
127 | } | 127 | } |
128 | 128 | ||
129 | TX0STAT = xfer_size; /* size of the transfer */ | 129 | TX0STAT = xfer_size; /* size of the transfer */ |
130 | TX0DMALM_IADDR = (uint32_t)ctrlep[DIR_IN].buf; /* local buffer address */ | 130 | TX0DMALM_IADDR = (uint32_t)ctrlep[DIR_IN].buf; /* local buffer address */ |
131 | TX0DMAINCTL = (1<<1); /* start DMA */ | 131 | TX0DMAINCTL = DMA_START; /* start DMA */ |
132 | TX0CON &= ~(1<<2); /* clear NAK */ | 132 | TX0CON &= ~TXNAK; /* clear NAK */ |
133 | 133 | ||
134 | /* Decrement by max packet size is intentional. | 134 | /* Decrement by max packet size is intentional. |
135 | * This way if we have final packet short one we will get negative len | 135 | * This way if we have final packet short one we will get negative len |
@@ -147,13 +147,13 @@ static void ctr_read(void) | |||
147 | int xfer_size = RX0STAT & 0xffff; | 147 | int xfer_size = RX0STAT & 0xffff; |
148 | 148 | ||
149 | /* clear NAK bit */ | 149 | /* clear NAK bit */ |
150 | RX0CON &= ~(1<<3); | 150 | RX0CON &= ~RXNAK; |
151 | 151 | ||
152 | ctrlep[DIR_OUT].cnt -= xfer_size; | 152 | ctrlep[DIR_OUT].cnt -= xfer_size; |
153 | ctrlep[DIR_OUT].buf += xfer_size; | 153 | ctrlep[DIR_OUT].buf += xfer_size; |
154 | 154 | ||
155 | RX0DMAOUTLMADDR = (uint32_t)ctrlep[DIR_OUT].buf; | 155 | RX0DMAOUTLMADDR = (uint32_t)ctrlep[DIR_OUT].buf; /* buffer address */ |
156 | RX0DMACTLO = (1<<0); | 156 | RX0DMACTLO = DMA_START; /* start DMA */ |
157 | } | 157 | } |
158 | 158 | ||
159 | static void blk_write(int ep) | 159 | static void blk_write(int ep) |
@@ -163,16 +163,16 @@ static void blk_write(int ep) | |||
163 | int xfer_size = (endpoints[ep_num].cnt > max) ? max : endpoints[ep_num].cnt; | 163 | int xfer_size = (endpoints[ep_num].cnt > max) ? max : endpoints[ep_num].cnt; |
164 | unsigned int timeout = current_tick + HZ/10; | 164 | unsigned int timeout = current_tick + HZ/10; |
165 | 165 | ||
166 | while (BIN_TXBUF(ep_num) & (1<<0)) /* TXFULL flag */ | 166 | while (BIN_TXBUF(ep_num) & TXFULL) /* TXFULL flag */ |
167 | { | 167 | { |
168 | if(TIME_AFTER(current_tick, timeout)) | 168 | if(TIME_AFTER(current_tick, timeout)) |
169 | break; | 169 | break; |
170 | } | 170 | } |
171 | 171 | ||
172 | BIN_TXSTAT(ep_num) = xfer_size; /* size of the transfer */ | 172 | BIN_TXSTAT(ep_num) = xfer_size; /* size */ |
173 | BIN_DMAINLMADDR(ep_num) = (uint32_t)endpoints[ep_num].buf; /* buf address */ | 173 | BIN_DMAINLMADDR(ep_num) = (uint32_t)endpoints[ep_num].buf; /* buf address */ |
174 | BIN_DMAINCTL(ep_num) = (1<<0); /* start DMA */ | 174 | BIN_DMAINCTL(ep_num) = DMA_START; /* start DMA */ |
175 | BIN_TXCON(ep_num) &= ~(1<<2); /* clear NAK */ | 175 | BIN_TXCON(ep_num) &= ~TXNAK; /* clear NAK */ |
176 | 176 | ||
177 | /* Decrement by max packet size is intentional. | 177 | /* Decrement by max packet size is intentional. |
178 | * This way if we have final packet short one we will get negative len | 178 | * This way if we have final packet short one we will get negative len |
@@ -191,13 +191,13 @@ static void blk_read(int ep) | |||
191 | int xfer_size = BOUT_RXSTAT(ep_num) & 0xffff; | 191 | int xfer_size = BOUT_RXSTAT(ep_num) & 0xffff; |
192 | 192 | ||
193 | /* clear NAK bit */ | 193 | /* clear NAK bit */ |
194 | BOUT_RXCON(ep_num) &= ~(1<<3); | 194 | BOUT_RXCON(ep_num) &= ~RXNAK; |
195 | 195 | ||
196 | endpoints[ep_num].cnt -= xfer_size; | 196 | endpoints[ep_num].cnt -= xfer_size; |
197 | endpoints[ep_num].buf += xfer_size; | 197 | endpoints[ep_num].buf += xfer_size; |
198 | 198 | ||
199 | BOUT_DMAOUTLMADDR(ep_num) = (uint32_t)endpoints[ep_num].buf; | 199 | BOUT_DMAOUTLMADDR(ep_num) = (uint32_t)endpoints[ep_num].buf; |
200 | BOUT_DMAOUTCTL(ep_num) = (1<<1); | 200 | BOUT_DMAOUTCTL(ep_num) = DMA_START; |
201 | } | 201 | } |
202 | 202 | ||
203 | static void int_write(int ep) | 203 | static void int_write(int ep) |
@@ -207,16 +207,16 @@ static void int_write(int ep) | |||
207 | int xfer_size = (endpoints[ep_num].cnt > max) ? max : endpoints[ep_num].cnt; | 207 | int xfer_size = (endpoints[ep_num].cnt > max) ? max : endpoints[ep_num].cnt; |
208 | unsigned int timeout = current_tick + HZ/10; | 208 | unsigned int timeout = current_tick + HZ/10; |
209 | 209 | ||
210 | while (IIN_TXBUF(ep_num) & (1<<0)) /* TXFULL flag */ | 210 | while (IIN_TXBUF(ep_num) & TXFULL) /* TXFULL flag */ |
211 | { | 211 | { |
212 | if(TIME_AFTER(current_tick, timeout)) | 212 | if(TIME_AFTER(current_tick, timeout)) |
213 | break; | 213 | break; |
214 | } | 214 | } |
215 | 215 | ||
216 | IIN_TXSTAT(ep_num) = xfer_size; /* size of the transfer */ | 216 | IIN_TXSTAT(ep_num) = xfer_size; /* size */ |
217 | IIN_DMAINLMADDR(ep_num) = (uint32_t)endpoints[ep_num].buf; /* buf address */ | 217 | IIN_DMAINLMADDR(ep_num) = (uint32_t)endpoints[ep_num].buf; /* buf address */ |
218 | IIN_DMAINCTL(ep_num) = (1<<0); /* start DMA */ | 218 | IIN_DMAINCTL(ep_num) = DMA_START; /* start DMA */ |
219 | IIN_TXCON(ep_num) &= ~(1<<2); /* clear NAK */ | 219 | IIN_TXCON(ep_num) &= ~TXNAK; /* clear NAK */ |
220 | 220 | ||
221 | /* Decrement by max packet size is intentional. | 221 | /* Decrement by max packet size is intentional. |
222 | * This way if we have final packet short one we will get negative len | 222 | * This way if we have final packet short one we will get negative len |
@@ -238,16 +238,16 @@ void INT_UDC(void) | |||
238 | /* read what caused UDC irq */ | 238 | /* read what caused UDC irq */ |
239 | uint32_t intsrc = INT2FLAG & 0x7fffff; | 239 | uint32_t intsrc = INT2FLAG & 0x7fffff; |
240 | 240 | ||
241 | if (intsrc & (1<<1)) /* setup interrupt */ | 241 | if (intsrc & SETUP_INTR) /* setup interrupt */ |
242 | { | 242 | { |
243 | setup_received(); | 243 | setup_received(); |
244 | } | 244 | } |
245 | else if (intsrc & (1<<2)) /* ep0 in interrupt */ | 245 | else if (intsrc & IN0_INTR) /* ep0 in interrupt */ |
246 | { | 246 | { |
247 | txstat = TX0STAT; /* read clears flags */ | 247 | txstat = TX0STAT; /* read clears flags */ |
248 | 248 | ||
249 | /* TODO handle errors */ | 249 | /* TODO handle errors */ |
250 | if (txstat & (1<<18)) /* check TxACK flag */ | 250 | if (txstat & TXACK) /* check TxACK flag */ |
251 | { | 251 | { |
252 | if (ctrlep[DIR_IN].cnt >= 0) | 252 | if (ctrlep[DIR_IN].cnt >= 0) |
253 | { | 253 | { |
@@ -268,12 +268,12 @@ void INT_UDC(void) | |||
268 | } | 268 | } |
269 | } | 269 | } |
270 | } | 270 | } |
271 | else if (intsrc & (1<<3)) /* ep0 out interrupt */ | 271 | else if (intsrc & OUT0_INTR) /* ep0 out interrupt */ |
272 | { | 272 | { |
273 | rxstat = RX0STAT; | 273 | rxstat = RX0STAT; |
274 | 274 | ||
275 | /* TODO handle errors */ | 275 | /* TODO handle errors */ |
276 | if (rxstat & (1<<18)) /* RxACK */ | 276 | if (rxstat & RXACK) /* RxACK */ |
277 | { | 277 | { |
278 | if (ctrlep[DIR_OUT].cnt > 0) | 278 | if (ctrlep[DIR_OUT].cnt > 0) |
279 | ctr_read(); | 279 | ctr_read(); |
@@ -284,21 +284,21 @@ void INT_UDC(void) | |||
284 | ctrlep[DIR_OUT].len); /* length */ | 284 | ctrlep[DIR_OUT].len); /* length */ |
285 | } | 285 | } |
286 | } | 286 | } |
287 | else if (intsrc & (1<<4)) /* usb reset */ | 287 | else if (intsrc & USBRST_INTR) /* usb reset */ |
288 | { | 288 | { |
289 | usb_drv_init(); | 289 | usb_drv_init(); |
290 | } | 290 | } |
291 | else if (intsrc & (1<<5)) /* usb resume */ | 291 | else if (intsrc & RESUME_INTR) /* usb resume */ |
292 | { | 292 | { |
293 | TX0CON |= (1<<0); /* TxClr */ | 293 | TX0CON |= TXCLR; /* TxClr */ |
294 | TX0CON &= ~(1<<0); | 294 | TX0CON &= ~TXCLR; |
295 | RX0CON |= (1<<1); /* RxClr */ | 295 | RX0CON |= RXCLR; /* RxClr */ |
296 | RX0CON &= (1<<1); | 296 | RX0CON &= ~RXCLR; |
297 | } | 297 | } |
298 | else if (intsrc & (1<<6)) /* usb suspend */ | 298 | else if (intsrc & SUSP_INTR) /* usb suspend */ |
299 | { | 299 | { |
300 | } | 300 | } |
301 | else if (intsrc & (1<<7)) /* usb connect */ | 301 | else if (intsrc & CONN_INTR) /* usb connect */ |
302 | { | 302 | { |
303 | } | 303 | } |
304 | else | 304 | else |
@@ -362,7 +362,7 @@ void INT_UDC(void) | |||
362 | txstat = IIN_TXSTAT(ep_num); | 362 | txstat = IIN_TXSTAT(ep_num); |
363 | 363 | ||
364 | /* TODO handle errors */ | 364 | /* TODO handle errors */ |
365 | if (txstat & (1<<18)) /* check TxACK flag */ | 365 | if (txstat & TXACK) /* check TxACK flag */ |
366 | { | 366 | { |
367 | if (endpoints[ep_num].cnt >= 0) | 367 | if (endpoints[ep_num].cnt >= 0) |
368 | { | 368 | { |
@@ -389,7 +389,7 @@ void INT_UDC(void) | |||
389 | /* return port speed FS=0, HS=1 */ | 389 | /* return port speed FS=0, HS=1 */ |
390 | int usb_drv_port_speed(void) | 390 | int usb_drv_port_speed(void) |
391 | { | 391 | { |
392 | return ((DEV_INFO & (3<<21)) == 0) ? 0 : 1; | 392 | return ((DEV_INFO & DEV_SPEED) == 0) ? 0 : 1; |
393 | } | 393 | } |
394 | 394 | ||
395 | /* Reserve endpoint */ | 395 | /* Reserve endpoint */ |
@@ -521,9 +521,9 @@ int usb_drv_recv(int endpoint, void* ptr, int length) | |||
521 | ep = &endpoints[ep_num]; | 521 | ep = &endpoints[ep_num]; |
522 | 522 | ||
523 | /* clear NAK bit */ | 523 | /* clear NAK bit */ |
524 | BOUT_RXCON(ep_num) &= ~(1<<3); | 524 | BOUT_RXCON(ep_num) &= ~RXNAK; |
525 | BOUT_DMAOUTLMADDR(ep_num) = (uint32_t)ptr; | 525 | BOUT_DMAOUTLMADDR(ep_num) = (uint32_t)ptr; |
526 | BOUT_DMAOUTCTL(ep_num) = (1<<1); | 526 | BOUT_DMAOUTCTL(ep_num) = DMA_START; |
527 | } | 527 | } |
528 | 528 | ||
529 | ep->buf = ptr; | 529 | ep->buf = ptr; |
@@ -557,23 +557,23 @@ bool usb_drv_stalled(int endpoint, bool in) | |||
557 | { | 557 | { |
558 | case USB_ENDPOINT_XFER_CONTROL: | 558 | case USB_ENDPOINT_XFER_CONTROL: |
559 | if (in) | 559 | if (in) |
560 | return (TX0CON & (1<<1)) ? true : false; | 560 | return (TX0CON & TXSTALL) ? true : false; |
561 | else | 561 | else |
562 | return (RX0CON & (1<<2)) ? true : false; | 562 | return (RX0CON & RXSTALL) ? true : false; |
563 | 563 | ||
564 | break; | 564 | break; |
565 | 565 | ||
566 | case USB_ENDPOINT_XFER_BULK: | 566 | case USB_ENDPOINT_XFER_BULK: |
567 | if (in) | 567 | if (in) |
568 | return (BIN_TXCON(ep_num) & (1<<1)) ? true : false; | 568 | return (BIN_TXCON(ep_num) & TXSTALL) ? true : false; |
569 | else | 569 | else |
570 | return (BOUT_RXCON(ep_num) & (1<<2)) ? true : false; | 570 | return (BOUT_RXCON(ep_num) & RXSTALL) ? true : false; |
571 | 571 | ||
572 | break; | 572 | break; |
573 | 573 | ||
574 | case USB_ENDPOINT_XFER_INT: | 574 | case USB_ENDPOINT_XFER_INT: |
575 | if (in) | 575 | if (in) |
576 | return (IIN_TXCON(ep_num) & (1<<1)) ? true : false; | 576 | return (IIN_TXCON(ep_num) & TXSTALL) ? true : false; |
577 | else | 577 | else |
578 | return false; /* we don't have such endpoint anyway */ | 578 | return false; /* we don't have such endpoint anyway */ |
579 | 579 | ||
@@ -594,16 +594,16 @@ void usb_drv_stall(int endpoint, bool stall, bool in) | |||
594 | if (in) | 594 | if (in) |
595 | { | 595 | { |
596 | if (stall) | 596 | if (stall) |
597 | TX0CON |= (1<<1); | 597 | TX0CON |= TXSTALL; |
598 | else | 598 | else |
599 | TX0CON &= ~(1<<1); | 599 | TX0CON &= ~TXSTALL; |
600 | } | 600 | } |
601 | else | 601 | else |
602 | { | 602 | { |
603 | if (stall) | 603 | if (stall) |
604 | RX0CON |= (1<<2); | 604 | RX0CON |= RXSTALL; |
605 | else | 605 | else |
606 | RX0CON &= ~(1<<2); /* doc says Auto clear by UDC 2.0 */ | 606 | RX0CON &= ~RXSTALL; /* doc says Auto clear by UDC 2.0 */ |
607 | } | 607 | } |
608 | break; | 608 | break; |
609 | 609 | ||
@@ -611,16 +611,16 @@ void usb_drv_stall(int endpoint, bool stall, bool in) | |||
611 | if (in) | 611 | if (in) |
612 | { | 612 | { |
613 | if (stall) | 613 | if (stall) |
614 | BIN_TXCON(ep_num) |= (1<<1); | 614 | BIN_TXCON(ep_num) |= TXSTALL; |
615 | else | 615 | else |
616 | BIN_TXCON(ep_num) &= ~(1<<1); | 616 | BIN_TXCON(ep_num) &= ~TXSTALL; |
617 | } | 617 | } |
618 | else | 618 | else |
619 | { | 619 | { |
620 | if (stall) | 620 | if (stall) |
621 | BOUT_RXCON(ep_num) |= (1<<2); | 621 | BOUT_RXCON(ep_num) |= RXSTALL; |
622 | else | 622 | else |
623 | BOUT_RXCON(ep_num) &= ~(1<<2); | 623 | BOUT_RXCON(ep_num) &= ~RXSTALL; |
624 | } | 624 | } |
625 | break; | 625 | break; |
626 | 626 | ||
@@ -628,9 +628,9 @@ void usb_drv_stall(int endpoint, bool stall, bool in) | |||
628 | if (in) | 628 | if (in) |
629 | { | 629 | { |
630 | if (stall) | 630 | if (stall) |
631 | IIN_TXCON(ep_num) |= (1<<1); | 631 | IIN_TXCON(ep_num) |= TXSTALL; |
632 | else | 632 | else |
633 | IIN_TXCON(ep_num) &= ~(1<<1); | 633 | IIN_TXCON(ep_num) &= ~TXSTALL; |
634 | } | 634 | } |
635 | break; | 635 | break; |
636 | } | 636 | } |
@@ -645,46 +645,46 @@ void usb_drv_init(void) | |||
645 | SCU_CLKCFG &= ~(1<<6); | 645 | SCU_CLKCFG &= ~(1<<6); |
646 | 646 | ||
647 | /* 1. do soft disconnect */ | 647 | /* 1. do soft disconnect */ |
648 | DEV_CTL = (1<<3); /* DEV_SELF_PWR */ | 648 | DEV_CTL = DEV_SELF_PWR; |
649 | 649 | ||
650 | /* 2. do power on reset to PHY */ | 650 | /* 2. do power on reset to PHY */ |
651 | DEV_CTL = (1<<3) | /* DEV_SELF_PWR */ | 651 | DEV_CTL = DEV_SELF_PWR | |
652 | (1<<7); /* SOFT_POR */ | 652 | SOFT_POR; |
653 | 653 | ||
654 | /* 3. wait more than 10ms */ | 654 | /* 3. wait more than 10ms */ |
655 | udelay(20000); | 655 | udelay(20000); |
656 | 656 | ||
657 | /* 4. clear SOFT_POR bit */ | 657 | /* 4. clear SOFT_POR bit */ |
658 | DEV_CTL &= ~(1<<7); | 658 | DEV_CTL &= ~SOFT_POR; |
659 | 659 | ||
660 | /* 5. configure minimal EN_INT */ | 660 | /* 5. configure minimal EN_INT */ |
661 | EN_INT = (1<<6) | /* Enable Suspend Interrupt */ | 661 | EN_INT = EN_SUSP_INTR | /* Enable Suspend Interrupt */ |
662 | (1<<5) | /* Enable Resume Interrupt */ | 662 | EN_RESUME_INTR | /* Enable Resume Interrupt */ |
663 | (1<<4) | /* Enable USB Reset Interrupt */ | 663 | EN_USBRST_INTR | /* Enable USB Reset Interrupt */ |
664 | (1<<3) | /* Enable OUT Token receive Interrupt EP0 */ | 664 | EN_OUT0_INTR | /* Enable OUT Token receive Interrupt EP0 */ |
665 | (1<<2) | /* Enable IN Token transmits Interrupt EP0 */ | 665 | EN_IN0_INTR | /* Enable IN Token transmits Interrupt EP0 */ |
666 | (1<<1); /* Enable SETUP Packet Receive Interrupt */ | 666 | EN_SETUP_INTR; /* Enable SETUP Packet Receive Interrupt */ |
667 | 667 | ||
668 | /* 6. configure INTCON */ | 668 | /* 6. configure INTCON */ |
669 | INTCON = (1<<2) | /* interrupt high active */ | 669 | INTCON = UDC_INTHIGH_ACT | /* interrupt high active */ |
670 | (1<<0); /* enable EP0 interrupts */ | 670 | UDC_INTEN; /* enable EP0 interrupts */ |
671 | 671 | ||
672 | /* 7. configure EP0 control registers */ | 672 | /* 7. configure EP0 control registers */ |
673 | TX0CON = (1<<6) | /* Set as one to enable the EP0 tx irq */ | 673 | TX0CON = TXACKINTEN | /* Set as one to enable the EP0 tx irq */ |
674 | (1<<2); /* Set as one to response NAK handshake */ | 674 | TXNAK; /* Set as one to response NAK handshake */ |
675 | 675 | ||
676 | RX0CON = (1<<7) | | 676 | RX0CON = RXACKINTEN | |
677 | (1<<4) | /* Endpoint 0 Enable. When cleared the endpoint does | 677 | RXEPEN | /* Endpoint 0 Enable. When cleared the endpoint does |
678 | * not respond to an SETUP or OUT token | 678 | * not respond to an SETUP or OUT token |
679 | */ | 679 | */ |
680 | 680 | ||
681 | (1<<3); /* Set as one to response NAK handshake */ | 681 | RXNAK; /* Set as one to response NAK handshake */ |
682 | 682 | ||
683 | /* 8. write final bits to DEV_CTL */ | 683 | /* 8. write final bits to DEV_CTL */ |
684 | DEV_CTL = (1<<8) | /* Configure CSR done */ | 684 | DEV_CTL = CSR_DONE | /* Configure CSR done */ |
685 | (1<<6) | /* 16-bit data path enabled. udc_clk = 30MHz */ | 685 | DEV_PHY16BIT | /* 16-bit data path enabled. udc_clk = 30MHz */ |
686 | (1<<4) | /* Device soft connect */ | 686 | DEV_SOFT_CN | /* Device soft connect */ |
687 | (1<<3); /* Device self power */ | 687 | DEV_SELF_PWR; /* Device self power */ |
688 | 688 | ||
689 | /* init semaphore of ep0 */ | 689 | /* init semaphore of ep0 */ |
690 | semaphore_init(&ctrlep[DIR_OUT].complete, 1, 0); | 690 | semaphore_init(&ctrlep[DIR_OUT].complete, 1, 0); |
@@ -696,15 +696,15 @@ void usb_drv_init(void) | |||
696 | 696 | ||
697 | if (ep_num%3 == 0) /* IIN 3, 6, 9, 12, 15 */ | 697 | if (ep_num%3 == 0) /* IIN 3, 6, 9, 12, 15 */ |
698 | { | 698 | { |
699 | IIN_TXCON(ep_num) |= (ep_num<<8)|(1<<3)|(1<<2); /* ep_num, enable, NAK */ | 699 | IIN_TXCON(ep_num) |= (ep_num<<8)|TXEPEN|TXNAK; /* ep_num, enable, NAK */ |
700 | } | 700 | } |
701 | else if (ep_num%3 == 1) /* BOUT 1, 4, 7, 10, 13 */ | 701 | else if (ep_num%3 == 1) /* BOUT 1, 4, 7, 10, 13 */ |
702 | { | 702 | { |
703 | BOUT_RXCON(ep_num) |= (ep_num<<8)|(1<<4)|(1<<3); /* ep_num, NAK, enable */ | 703 | BOUT_RXCON(ep_num) |= (ep_num<<8)|RXEPEN|RXNAK; /* ep_num, NAK, enable */ |
704 | } | 704 | } |
705 | else if (ep_num%3 == 2) /* BIN 2, 5, 8, 11, 14 */ | 705 | else if (ep_num%3 == 2) /* BIN 2, 5, 8, 11, 14 */ |
706 | { | 706 | { |
707 | BIN_TXCON(ep_num) |= (ep_num<<8)|(1<<3)|(1<<2); /* ep_num, enable, NAK */ | 707 | BIN_TXCON(ep_num) |= (ep_num<<8)|TXEPEN|TXNAK; /* ep_num, enable, NAK */ |
708 | } | 708 | } |
709 | } | 709 | } |
710 | } | 710 | } |
@@ -712,7 +712,7 @@ void usb_drv_init(void) | |||
712 | /* turn off usb core */ | 712 | /* turn off usb core */ |
713 | void usb_drv_exit(void) | 713 | void usb_drv_exit(void) |
714 | { | 714 | { |
715 | DEV_CTL = (1<<3); /* DEV_SELF_PWR */ | 715 | DEV_CTL = DEV_SELF_PWR; |
716 | 716 | ||
717 | /* disable USB interrupts in interrupt controller */ | 717 | /* disable USB interrupts in interrupt controller */ |
718 | INTC_IMR &= ~(1<<16); | 718 | INTC_IMR &= ~(1<<16); |
@@ -725,7 +725,7 @@ void usb_drv_exit(void) | |||
725 | 725 | ||
726 | int usb_detect(void) | 726 | int usb_detect(void) |
727 | { | 727 | { |
728 | if (DEV_INFO & (1<<20)) | 728 | if (DEV_INFO & VBUS_STS) |
729 | return USB_INSERTED; | 729 | return USB_INSERTED; |
730 | else | 730 | else |
731 | return USB_EXTRACTED; | 731 | return USB_EXTRACTED; |