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author | Michael Sevakis <jethead71@rockbox.org> | 2008-04-21 21:45:58 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2008-04-21 21:45:58 +0000 |
commit | 8ec1dca0da5d4d2d4d81768ab31ccb2f0981aadc (patch) | |
tree | c2499d770aa402eb49da4366dca549265134a575 /firmware/target/arm | |
parent | 5818bc3c3102c64a39e4fb6bf878841255753225 (diff) | |
download | rockbox-8ec1dca0da5d4d2d4d81768ab31ccb2f0981aadc.tar.gz rockbox-8ec1dca0da5d4d2d4d81768ab31ccb2f0981aadc.zip |
Enable program flow prediction in the system control coprocessor setup in the bootloader.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17211 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/imx31/crt0.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S index ab8e5199e2..d982b91608 100644 --- a/firmware/target/arm/imx31/crt0.S +++ b/firmware/target/arm/imx31/crt0.S | |||
@@ -198,10 +198,10 @@ remap_start: | |||
198 | (1 << 22)) /* Unaligned access support disabled */ | 198 | (1 << 22)) /* Unaligned access support disabled */ |
199 | bic r0, r0, #((1 << 21) | /* All performance features enabled */ \ | 199 | bic r0, r0, #((1 << 21) | /* All performance features enabled */ \ |
200 | (1 << 15)) /* Loads to PC set T bit */ | 200 | (1 << 15)) /* Loads to PC set T bit */ |
201 | bic r0, r0, #((1 << 13) | /* Low vectors */ \ | 201 | bic r0, r0, #((1 << 13)) /* Low vectors */ |
202 | (1 << 11)) /* Program flow prediction disabled (for now) */ | ||
203 | orr r0, r0, #((1 << 14) | /* Round-robin replacement for I/D caches */ \ | 202 | orr r0, r0, #((1 << 14) | /* Round-robin replacement for I/D caches */ \ |
204 | (1 << 12) | /* L1 I-cache enabled */ \ | 203 | (1 << 12) | /* L1 I-cache enabled */ \ |
204 | (1 << 11) | /* Program flow prediction enabled */ \ | ||
205 | (1 << 9) | /* ROM protection enabled */ \ | 205 | (1 << 9) | /* ROM protection enabled */ \ |
206 | (1 << 8)) /* MMU protection enabled */ | 206 | (1 << 8)) /* MMU protection enabled */ |
207 | orr r0, r0, #((1 << 2) | /* L1 D-cache enabled */ \ | 207 | orr r0, r0, #((1 << 2) | /* L1 D-cache enabled */ \ |