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authorAmaury Pouly <amaury.pouly@gmail.com>2013-06-16 16:46:12 +0200
committerAmaury Pouly <amaury.pouly@gmail.com>2013-06-16 16:58:00 +0200
commit6f0eaf482714d4a17a6d68abdb83121bbf78f501 (patch)
tree039ee4039619bfb1cd1f40d0123a13e21832d9a8 /firmware/target/arm
parentd815cf3c79321eb5db66cd18a77e3713943560a8 (diff)
downloadrockbox-6f0eaf482714d4a17a6d68abdb83121bbf78f501.tar.gz
rockbox-6f0eaf482714d4a17a6d68abdb83121bbf78f501.zip
imx233: rewrite ocotp using new register headers
Change-Id: I3c622119a1e296ec6b3f35f27e81b5118ab7f6cc
Diffstat (limited to 'firmware/target/arm')
-rw-r--r--firmware/target/arm/imx233/debug-imx233.c26
-rw-r--r--firmware/target/arm/imx233/ocotp-imx233.h37
2 files changed, 21 insertions, 42 deletions
diff --git a/firmware/target/arm/imx233/debug-imx233.c b/firmware/target/arm/imx233/debug-imx233.c
index 292cb2e9e2..10f951c2e1 100644
--- a/firmware/target/arm/imx233/debug-imx233.c
+++ b/firmware/target/arm/imx233/debug-imx233.c
@@ -557,20 +557,20 @@ struct
557} dbg_ocotp[] = 557} dbg_ocotp[] =
558{ 558{
559#define E(n,v) { .name = n, .addr = &v } 559#define E(n,v) { .name = n, .addr = &v }
560 E("CUST0", HW_OCOTP_CUSTx(0)), E("CUST1", HW_OCOTP_CUSTx(1)), 560 E("CUST0", HW_OCOTP_CUSTn(0)), E("CUST1", HW_OCOTP_CUSTn(1)),
561 E("CUST2", HW_OCOTP_CUSTx(2)), E("CUST0", HW_OCOTP_CUSTx(3)), 561 E("CUST2", HW_OCOTP_CUSTn(2)), E("CUST0", HW_OCOTP_CUSTn(3)),
562 E("HWCAP0", HW_OCOTP_HWCAPx(0)), E("HWCAP1", HW_OCOTP_HWCAPx(1)), 562 E("HWCAP0", HW_OCOTP_HWCAPn(0)), E("HWCAP1", HW_OCOTP_HWCAPn(1)),
563 E("HWCAP2", HW_OCOTP_HWCAPx(2)), E("HWCAP3", HW_OCOTP_HWCAPx(3)), 563 E("HWCAP2", HW_OCOTP_HWCAPn(2)), E("HWCAP3", HW_OCOTP_HWCAPn(3)),
564 E("HWCAP4", HW_OCOTP_HWCAPx(4)), E("HWCAP5", HW_OCOTP_HWCAPx(5)), 564 E("HWCAP4", HW_OCOTP_HWCAPn(4)), E("HWCAP5", HW_OCOTP_HWCAPn(5)),
565 E("SWCAP", HW_OCOTP_SWCAP), E("CUSTCAP", HW_OCOTP_CUSTCAP), 565 E("SWCAP", HW_OCOTP_SWCAP), E("CUSTCAP", HW_OCOTP_CUSTCAP),
566 E("OPS0", HW_OCOTP_OPSx(0)), E("OPS1", HW_OCOTP_OPSx(1)), 566 E("OPS0", HW_OCOTP_OPSn(0)), E("OPS1", HW_OCOTP_OPSn(1)),
567 E("OPS2", HW_OCOTP_OPSx(2)), E("OPS2", HW_OCOTP_OPSx(3)), 567 E("OPS2", HW_OCOTP_OPSn(2)), E("OPS2", HW_OCOTP_OPSn(3)),
568 E("UN0", HW_OCOTP_UNx(0)), E("UN1", HW_OCOTP_UNx(1)), 568 E("UN0", HW_OCOTP_UNn(0)), E("UN1", HW_OCOTP_UNn(1)),
569 E("UN2", HW_OCOTP_UNx(2)), 569 E("UN2", HW_OCOTP_UNn(2)),
570 E("ROM0", HW_OCOTP_ROMx(0)), E("ROM1", HW_OCOTP_ROMx(1)), 570 E("ROM0", HW_OCOTP_ROMn(0)), E("ROM1", HW_OCOTP_ROMn(1)),
571 E("ROM2", HW_OCOTP_ROMx(2)), E("ROM3", HW_OCOTP_ROMx(3)), 571 E("ROM2", HW_OCOTP_ROMn(2)), E("ROM3", HW_OCOTP_ROMn(3)),
572 E("ROM4", HW_OCOTP_ROMx(4)), E("ROM5", HW_OCOTP_ROMx(5)), 572 E("ROM4", HW_OCOTP_ROMn(4)), E("ROM5", HW_OCOTP_ROMn(5)),
573 E("ROM6", HW_OCOTP_ROMx(6)), E("ROM7", HW_OCOTP_ROMx(7)), 573 E("ROM6", HW_OCOTP_ROMn(6)), E("ROM7", HW_OCOTP_ROMn(7)),
574}; 574};
575 575
576bool dbg_hw_info_ocotp(void) 576bool dbg_hw_info_ocotp(void)
diff --git a/firmware/target/arm/imx233/ocotp-imx233.h b/firmware/target/arm/imx233/ocotp-imx233.h
index 476ed1f73c..9406f98530 100644
--- a/firmware/target/arm/imx233/ocotp-imx233.h
+++ b/firmware/target/arm/imx233/ocotp-imx233.h
@@ -24,28 +24,7 @@
24#include "config.h" 24#include "config.h"
25#include "system.h" 25#include "system.h"
26 26
27#define HW_OCOTP_BASE 0x8002c000 27#include "regs/regs-ocotp.h"
28
29#define HW_OCOTP_CTRL (*(volatile uint32_t *)(HW_OCOTP_BASE + 0x0))
30#define HW_OCOTP_CTRL__RD_BANK_OPEN (1 << 12)
31#define HW_OCOTP_CTRL__ERROR (1 << 9)
32#define HW_OCOTP_CTRL__BUSY (1 << 8)
33
34#define HW_OCOTP_CUSTx(x) (*(volatile uint32_t *)(HW_OCOTP_BASE + 0x20 + 0x10 * (x)))
35
36#define HW_OCOTP_CRYPTOx(x) (*(volatile uint32_t *)(HW_OCOTP_BASE + 0x60 + 0x10 * (x)))
37
38#define HW_OCOTP_HWCAPx(x) (*(volatile uint32_t *)(HW_OCOTP_BASE + 0xa0 + 0x10 * (x)))
39
40#define HW_OCOTP_SWCAP (*(volatile uint32_t *)(HW_OCOTP_BASE + 0x100))
41
42#define HW_OCOTP_CUSTCAP (*(volatile uint32_t *)(HW_OCOTP_BASE + 0x110))
43
44#define HW_OCOTP_OPSx(x) (*(volatile uint32_t *)(HW_OCOTP_BASE + 0x130 + 0x10 * (x)))
45
46#define HW_OCOTP_UNx(x) (*(volatile uint32_t *)(HW_OCOTP_BASE + 0x170 + 0x10 * (x)))
47
48#define HW_OCOTP_ROMx(x) (*(volatile uint32_t *)(HW_OCOTP_BASE + 0x1a0 + 0x10 * (x)))
49 28
50#define IMX233_NUM_OCOTP_CUST 4 29#define IMX233_NUM_OCOTP_CUST 4
51#define IMX233_NUM_OCOTP_CRYPTO 4 30#define IMX233_NUM_OCOTP_CRYPTO 4
@@ -54,19 +33,19 @@
54#define IMX233_NUM_OCOTP_UN 3 33#define IMX233_NUM_OCOTP_UN 3
55#define IMX233_NUM_OCOTP_ROM 8 34#define IMX233_NUM_OCOTP_ROM 8
56 35
57static void imx233_ocotp_open_banks(bool open) 36static inline void imx233_ocotp_open_banks(bool open)
58{ 37{
59 if(open) 38 if(open)
60 { 39 {
61 __REG_CLR(HW_OCOTP_CTRL) = HW_OCOTP_CTRL__ERROR; 40 BF_CLR(OCOTP_CTRL, ERROR);
62 __REG_SET(HW_OCOTP_CTRL) = HW_OCOTP_CTRL__RD_BANK_OPEN; 41 BF_SET(OCOTP_CTRL, RD_BANK_OPEN);
63 while(HW_OCOTP_CTRL & HW_OCOTP_CTRL__BUSY); 42 while(BF_RD(OCOTP_CTRL, BUSY));
64 } 43 }
65 else 44 else
66 __REG_CLR(HW_OCOTP_CTRL) = HW_OCOTP_CTRL__RD_BANK_OPEN; 45 BF_CLR(OCOTP_CTRL, RD_BANK_OPEN);
67} 46}
68 47
69static uint32_t imx233_ocotp_read(volatile uint32_t *reg) 48static inline uint32_t imx233_ocotp_read(volatile uint32_t *reg)
70{ 49{
71 imx233_ocotp_open_banks(true); 50 imx233_ocotp_open_banks(true);
72 uint32_t val = *reg; 51 uint32_t val = *reg;
@@ -74,4 +53,4 @@ static uint32_t imx233_ocotp_read(volatile uint32_t *reg)
74 return val; 53 return val;
75} 54}
76 55
77#endif /* OCOTP_IMX233_H */ 56#endif /* OCOTP_IMX233_H */ \ No newline at end of file