diff options
author | Will Robertson <aliask@rockbox.org> | 2007-12-23 12:19:40 +0000 |
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committer | Will Robertson <aliask@rockbox.org> | 2007-12-23 12:19:40 +0000 |
commit | 32f6109fb1df54ccdd5853883fd6b543a3d0a32a (patch) | |
tree | 001df8dac99109fa4faaad2e04db69a6a1a93f34 /firmware/target/arm | |
parent | a9933ce32ddabde8961de2601ab1a2f6d26d9b5a (diff) | |
download | rockbox-32f6109fb1df54ccdd5853883fd6b543a3d0a32a.tar.gz rockbox-32f6109fb1df54ccdd5853883fd6b543a3d0a32a.zip |
Gigabeat S memory management stuff.
* Moved crt0.S to imx31 subdirectory, as it was the last target using the unified file.
* DRAM is now remapped to 0x0, facilitating interrupts (which aren't done yet)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15965 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/imx31/crt0.S (renamed from firmware/target/arm/crt0.S) | 96 |
1 files changed, 72 insertions, 24 deletions
diff --git a/firmware/target/arm/crt0.S b/firmware/target/arm/imx31/crt0.S index c1bc9da059..2be2510bbd 100644 --- a/firmware/target/arm/crt0.S +++ b/firmware/target/arm/imx31/crt0.S | |||
@@ -35,12 +35,7 @@ start: | |||
35 | */ | 35 | */ |
36 | 36 | ||
37 | newstart: | 37 | newstart: |
38 | #if CONFIG_CPU == IMX31L | ||
39 | mov r0,#0xD3 | ||
40 | msr cpsr, r0 | ||
41 | #else | ||
42 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */ | 38 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */ |
43 | #endif | ||
44 | 39 | ||
45 | #if !defined(BOOTLOADER) | 40 | #if !defined(BOOTLOADER) |
46 | #if !defined(DEBUG) | 41 | #if !defined(DEBUG) |
@@ -60,11 +55,7 @@ newstart: | |||
60 | ldr r0, =fiq_handler | 55 | ldr r0, =fiq_handler |
61 | str r0, [r1, #28] | 56 | str r0, [r1, #28] |
62 | #endif | 57 | #endif |
63 | #endif | ||
64 | |||
65 | #if !defined(BOOTLOADER) | ||
66 | 58 | ||
67 | #if !defined(STUB) | ||
68 | /* Zero out IBSS */ | 59 | /* Zero out IBSS */ |
69 | ldr r2, =_iedata | 60 | ldr r2, =_iedata |
70 | ldr r3, =_iend | 61 | ldr r3, =_iend |
@@ -83,7 +74,6 @@ newstart: | |||
83 | ldrhi r5, [r2], #4 | 74 | ldrhi r5, [r2], #4 |
84 | strhi r5, [r3], #4 | 75 | strhi r5, [r3], #4 |
85 | bhi 1b | 76 | bhi 1b |
86 | #endif /* !STUB */ | ||
87 | #endif /* !BOOTLOADER */ | 77 | #endif /* !BOOTLOADER */ |
88 | 78 | ||
89 | /* Initialise bss section to zero */ | 79 | /* Initialise bss section to zero */ |
@@ -108,8 +98,6 @@ newstart: | |||
108 | #ifdef BOOTLOADER | 98 | #ifdef BOOTLOADER |
109 | /* Code for ARM bootloader targets other than iPod go here */ | 99 | /* Code for ARM bootloader targets other than iPod go here */ |
110 | 100 | ||
111 | #if CONFIG_CPU == IMX31L | ||
112 | |||
113 | mov r0, #0 | 101 | mov r0, #0 |
114 | mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ | 102 | mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ |
115 | mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ | 103 | mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ |
@@ -169,13 +157,83 @@ L2_loop: | |||
169 | mov r0,#0xd3 | 157 | mov r0,#0xd3 |
170 | msr cpsr, r0 | 158 | msr cpsr, r0 |
171 | ldr sp, =stackend | 159 | ldr sp, =stackend |
172 | 160 | ||
173 | /*remap memory as well as exception vectors*/ | 161 | /*remap memory as well as exception vectors*/ |
174 | /*for now this will be done in bootloader, especially | 162 | /*for now this will be done in bootloader, especially |
175 | if usb will be needed within the bootloader to load the | 163 | if usb will be needed within the bootloader to load the |
176 | main firmware file. Interrupts will be needed for this | 164 | main firmware file. Interrupts will be needed for this |
177 | (whether they be swi or irq)*/ | 165 | (whether they be swi or irq)*/ |
178 | bl memory_init | 166 | |
167 | /* TTB Initialisation */ | ||
168 | ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) | ||
169 | mov r1, #0 | ||
170 | ldr r2, =(0x80000000+64*1024*1024) | ||
171 | ttbloop: | ||
172 | str r1, [r3], #4 | ||
173 | cmp r3, r2 | ||
174 | bne ttbloop | ||
175 | |||
176 | /* Set TTB base address */ | ||
177 | ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) | ||
178 | mcr 15, 0 ,r3, cr2, cr0, 0 | ||
179 | /* Set all domains to manager status */ | ||
180 | mvn r3, #0 | ||
181 | mcr 15, 0, r3, cr3, cr0, 0 | ||
182 | |||
183 | /* Set page tables */ | ||
184 | |||
185 | /* Map each memory loc to itself, no cache */ | ||
186 | mov r1, #0 /* Physical address */ | ||
187 | ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) /* TTB pointer */ | ||
188 | ldr r4, =(0x80000000+64*1024*1024-TTB_SIZE+0x4000) /* End position */ | ||
189 | maploop1: | ||
190 | mov r2, r1 | ||
191 | orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */ | ||
192 | //orr r2, r2, #(0<<5) /* domain 0th */ | ||
193 | orr r2, r2, #(1<<4) /* should be "1" */ | ||
194 | orr r2, r2, #(1<<1) /* Section signature */ | ||
195 | str r2, [r3], #4 | ||
196 | add r1, r1, #(1<<20) | ||
197 | cmp r3, r4 | ||
198 | bne maploop1 | ||
199 | |||
200 | /* Map 0x80000000 -> 0x0, cached */ | ||
201 | mov r1, #0x80000000 /* Physical address */ | ||
202 | ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) /* TTB pointer */ | ||
203 | ldr r4, =(0x80000000+64*1024*1024-TTB_SIZE+256) /* End position */ | ||
204 | maploop2: | ||
205 | mov r2, r1 | ||
206 | orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */ | ||
207 | //orr r2, r2, #(0<<5) /* domain 0th */ | ||
208 | orr r2, r2, #(1<<4) /* should be "1" */ | ||
209 | orr r2, r2, #(1<<3) /* cache flags */ | ||
210 | orr r2, r2, #(1<<2) /* more cache stuff */ | ||
211 | orr r2, r2, #(1<<1) /* Section signature */ | ||
212 | str r2, [r3], #4 | ||
213 | add r1, r1, #(1<<20) | ||
214 | cmp r3, r4 | ||
215 | bne maploop2 | ||
216 | |||
217 | /* Enable MMU */ | ||
218 | mrc 15, 0, r3, cr1, cr0, 0 | ||
219 | tst r3, #0x4 | ||
220 | bleq clean_dcache | ||
221 | tst r3, #0x1000 | ||
222 | bleq clean_dcache | ||
223 | mov r0, #0 | ||
224 | |||
225 | mcr 15, 0, r0, cr8, cr7, 0 /* Invalidate TLB */ | ||
226 | mcr 15, 0, r0, cr7, cr7, 0 /* Invalidate icache and dcache */ | ||
227 | mrc 15, 0, r0, cr1, cr0, 0 | ||
228 | orr r0, r0, #1 /* enable mmu bit */ | ||
229 | orr r0, r0, #(1<<2) /* enable dcache */ | ||
230 | orr r0, r0, #(1<<12) /* enable icache */ | ||
231 | mcr 15, 0, r0, cr1, cr0, 0 | ||
232 | nop | ||
233 | nop | ||
234 | nop | ||
235 | nop | ||
236 | |||
179 | mov r0,#0 | 237 | mov r0,#0 |
180 | ldr r1,=_vectorstart | 238 | ldr r1,=_vectorstart |
181 | mov r2,#0 | 239 | mov r2,#0 |
@@ -253,7 +311,6 @@ irq_stack: | |||
253 | .space 256*4 | 311 | .space 256*4 |
254 | fiq_stack: | 312 | fiq_stack: |
255 | 313 | ||
256 | #endif | ||
257 | 314 | ||
258 | #else /* BOOTLOADER */ | 315 | #else /* BOOTLOADER */ |
259 | 316 | ||
@@ -276,9 +333,7 @@ fiq_stack: | |||
276 | /* main() should never return */ | 333 | /* main() should never return */ |
277 | 334 | ||
278 | /* Exception handlers. Will be copied to address 0 after memory remapping */ | 335 | /* Exception handlers. Will be copied to address 0 after memory remapping */ |
279 | #if CONFIG_CPU == IMX31L | ||
280 | _vectorstart: | 336 | _vectorstart: |
281 | #endif | ||
282 | .section .vectors,"aw" | 337 | .section .vectors,"aw" |
283 | ldr pc, [pc, #24] | 338 | ldr pc, [pc, #24] |
284 | ldr pc, [pc, #24] | 339 | ldr pc, [pc, #24] |
@@ -303,11 +358,9 @@ vectors: | |||
303 | 358 | ||
304 | .text | 359 | .text |
305 | 360 | ||
306 | #ifndef STUB | ||
307 | .global irq | 361 | .global irq |
308 | .global fiq | 362 | .global fiq |
309 | .global UIE | 363 | .global UIE |
310 | #endif | ||
311 | 364 | ||
312 | /* All illegal exceptions call into UIE with exception address as first | 365 | /* All illegal exceptions call into UIE with exception address as first |
313 | parameter. This is calculated differently depending on which exception | 366 | parameter. This is calculated differently depending on which exception |
@@ -336,11 +389,6 @@ data_abort_handler: | |||
336 | mov r1, #2 | 389 | mov r1, #2 |
337 | b UIE | 390 | b UIE |
338 | 391 | ||
339 | #ifdef STUB | ||
340 | UIE: | ||
341 | b UIE | ||
342 | #endif | ||
343 | |||
344 | /* 256 words of IRQ stack */ | 392 | /* 256 words of IRQ stack */ |
345 | .space 256*4 | 393 | .space 256*4 |
346 | irq_stack: | 394 | irq_stack: |