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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-12-06 02:04:37 +0100 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-12-06 02:04:37 +0100 |
commit | 2bf192ee6ed4d5d64155c5623faa09e063830c4c (patch) | |
tree | 795be3d5b9fa62c2320131666294e8632231b097 /firmware/target/arm | |
parent | e43bfdd5e80e30142d1880108f5439dead9dc7ea (diff) | |
download | rockbox-2bf192ee6ed4d5d64155c5623faa09e063830c4c.tar.gz rockbox-2bf192ee6ed4d5d64155c5623faa09e063830c4c.zip |
imx233: regenerate registers headers
Change-Id: I546177a247646d7a9864d1ec2796ef0708e50667
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/imx233/regs/regs-emi.h | 4 | ||||
-rw-r--r-- | firmware/target/arm/imx233/regs/stmp3600/regs-emi.h | 284 |
2 files changed, 287 insertions, 1 deletions
diff --git a/firmware/target/arm/imx233/regs/regs-emi.h b/firmware/target/arm/imx233/regs/regs-emi.h index 3f8a16ffbe..6ad4289631 100644 --- a/firmware/target/arm/imx233/regs/regs-emi.h +++ b/firmware/target/arm/imx233/regs/regs-emi.h | |||
@@ -7,7 +7,7 @@ | |||
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | 8 | * This file was automatically generated by headergen, DO NOT EDIT it. |
9 | * headergen version: 2.1.7 | 9 | * headergen version: 2.1.7 |
10 | * XML versions: stmp3700:3.2.0 imx233:3.2.0 | 10 | * XML versions: stmp3600:2.4.0 stmp3700:3.2.0 imx233:3.2.0 |
11 | * | 11 | * |
12 | * Copyright (C) 2013 by Amaury Pouly | 12 | * Copyright (C) 2013 by Amaury Pouly |
13 | * | 13 | * |
@@ -24,11 +24,13 @@ | |||
24 | #define __SELECT__EMI__H__ | 24 | #define __SELECT__EMI__H__ |
25 | #include "regs-macro.h" | 25 | #include "regs-macro.h" |
26 | 26 | ||
27 | #define STMP3600_INCLUDE "stmp3600/regs-emi.h" | ||
27 | #define STMP3700_INCLUDE "stmp3700/regs-emi.h" | 28 | #define STMP3700_INCLUDE "stmp3700/regs-emi.h" |
28 | #define IMX233_INCLUDE "imx233/regs-emi.h" | 29 | #define IMX233_INCLUDE "imx233/regs-emi.h" |
29 | 30 | ||
30 | #include "regs-select.h" | 31 | #include "regs-select.h" |
31 | 32 | ||
33 | #undef STMP3600_INCLUDE | ||
32 | #undef STMP3700_INCLUDE | 34 | #undef STMP3700_INCLUDE |
33 | #undef IMX233_INCLUDE | 35 | #undef IMX233_INCLUDE |
34 | 36 | ||
diff --git a/firmware/target/arm/imx233/regs/stmp3600/regs-emi.h b/firmware/target/arm/imx233/regs/stmp3600/regs-emi.h new file mode 100644 index 0000000000..25ad99e27c --- /dev/null +++ b/firmware/target/arm/imx233/regs/stmp3600/regs-emi.h | |||
@@ -0,0 +1,284 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 2.1.7 | ||
10 | * XML versions: stmp3600:2.4.0 | ||
11 | * | ||
12 | * Copyright (C) 2013 by Amaury Pouly | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef __HEADERGEN__STMP3600__EMI__H__ | ||
24 | #define __HEADERGEN__STMP3600__EMI__H__ | ||
25 | |||
26 | #define REGS_EMI_BASE (0x80020000) | ||
27 | |||
28 | #define REGS_EMI_VERSION "2.4.0" | ||
29 | |||
30 | /** | ||
31 | * Register: HW_EMI_CTRL | ||
32 | * Address: 0 | ||
33 | * SCT: yes | ||
34 | */ | ||
35 | #define HW_EMI_CTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x0)) | ||
36 | #define HW_EMI_CTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x4)) | ||
37 | #define HW_EMI_CTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0x8)) | ||
38 | #define HW_EMI_CTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x0 + 0xc)) | ||
39 | #define BP_EMI_CTRL_SFTRST 31 | ||
40 | #define BM_EMI_CTRL_SFTRST 0x80000000 | ||
41 | #define BF_EMI_CTRL_SFTRST(v) (((v) << 31) & 0x80000000) | ||
42 | #define BP_EMI_CTRL_CLKGATE 30 | ||
43 | #define BM_EMI_CTRL_CLKGATE 0x40000000 | ||
44 | #define BF_EMI_CTRL_CLKGATE(v) (((v) << 30) & 0x40000000) | ||
45 | #define BP_EMI_CTRL_CE3_MODE 3 | ||
46 | #define BM_EMI_CTRL_CE3_MODE 0x8 | ||
47 | #define BV_EMI_CTRL_CE3_MODE__STATIC 0x0 | ||
48 | #define BV_EMI_CTRL_CE3_MODE__DRAM 0x1 | ||
49 | #define BF_EMI_CTRL_CE3_MODE(v) (((v) << 3) & 0x8) | ||
50 | #define BF_EMI_CTRL_CE3_MODE_V(v) ((BV_EMI_CTRL_CE3_MODE__##v << 3) & 0x8) | ||
51 | #define BP_EMI_CTRL_CE2_MODE 2 | ||
52 | #define BM_EMI_CTRL_CE2_MODE 0x4 | ||
53 | #define BV_EMI_CTRL_CE2_MODE__STATIC 0x0 | ||
54 | #define BV_EMI_CTRL_CE2_MODE__DRAM 0x1 | ||
55 | #define BF_EMI_CTRL_CE2_MODE(v) (((v) << 2) & 0x4) | ||
56 | #define BF_EMI_CTRL_CE2_MODE_V(v) ((BV_EMI_CTRL_CE2_MODE__##v << 2) & 0x4) | ||
57 | #define BP_EMI_CTRL_CE1_MODE 1 | ||
58 | #define BM_EMI_CTRL_CE1_MODE 0x2 | ||
59 | #define BV_EMI_CTRL_CE1_MODE__STATIC 0x0 | ||
60 | #define BV_EMI_CTRL_CE1_MODE__DRAM 0x1 | ||
61 | #define BF_EMI_CTRL_CE1_MODE(v) (((v) << 1) & 0x2) | ||
62 | #define BF_EMI_CTRL_CE1_MODE_V(v) ((BV_EMI_CTRL_CE1_MODE__##v << 1) & 0x2) | ||
63 | #define BP_EMI_CTRL_CE0_MODE 0 | ||
64 | #define BM_EMI_CTRL_CE0_MODE 0x1 | ||
65 | #define BV_EMI_CTRL_CE0_MODE__STATIC 0x0 | ||
66 | #define BV_EMI_CTRL_CE0_MODE__DRAM 0x1 | ||
67 | #define BF_EMI_CTRL_CE0_MODE(v) (((v) << 0) & 0x1) | ||
68 | #define BF_EMI_CTRL_CE0_MODE_V(v) ((BV_EMI_CTRL_CE0_MODE__##v << 0) & 0x1) | ||
69 | |||
70 | /** | ||
71 | * Register: HW_EMI_STAT | ||
72 | * Address: 0x10 | ||
73 | * SCT: no | ||
74 | */ | ||
75 | #define HW_EMI_STAT (*(volatile unsigned long *)(REGS_EMI_BASE + 0x10)) | ||
76 | #define BP_EMI_STAT_DRAM_PRESENT 31 | ||
77 | #define BM_EMI_STAT_DRAM_PRESENT 0x80000000 | ||
78 | #define BF_EMI_STAT_DRAM_PRESENT(v) (((v) << 31) & 0x80000000) | ||
79 | #define BP_EMI_STAT_STATIC_PRESENT 30 | ||
80 | #define BM_EMI_STAT_STATIC_PRESENT 0x40000000 | ||
81 | #define BF_EMI_STAT_STATIC_PRESENT(v) (((v) << 30) & 0x40000000) | ||
82 | #define BP_EMI_STAT_LARGE_DRAM_ENABLED 29 | ||
83 | #define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000 | ||
84 | #define BF_EMI_STAT_LARGE_DRAM_ENABLED(v) (((v) << 29) & 0x20000000) | ||
85 | #define BP_EMI_STAT_WRITE_BUFFER_DATA 1 | ||
86 | #define BM_EMI_STAT_WRITE_BUFFER_DATA 0x2 | ||
87 | #define BV_EMI_STAT_WRITE_BUFFER_DATA__EMPTY 0x0 | ||
88 | #define BV_EMI_STAT_WRITE_BUFFER_DATA__NOT_EMPTY 0x1 | ||
89 | #define BF_EMI_STAT_WRITE_BUFFER_DATA(v) (((v) << 1) & 0x2) | ||
90 | #define BF_EMI_STAT_WRITE_BUFFER_DATA_V(v) ((BV_EMI_STAT_WRITE_BUFFER_DATA__##v << 1) & 0x2) | ||
91 | #define BP_EMI_STAT_BUSY 0 | ||
92 | #define BM_EMI_STAT_BUSY 0x1 | ||
93 | #define BV_EMI_STAT_BUSY__NOT_BUSY 0x0 | ||
94 | #define BV_EMI_STAT_BUSY__BUSY 0x1 | ||
95 | #define BF_EMI_STAT_BUSY(v) (((v) << 0) & 0x1) | ||
96 | #define BF_EMI_STAT_BUSY_V(v) ((BV_EMI_STAT_BUSY__##v << 0) & 0x1) | ||
97 | |||
98 | /** | ||
99 | * Register: HW_EMI_DEBUG | ||
100 | * Address: 0x20 | ||
101 | * SCT: no | ||
102 | */ | ||
103 | #define HW_EMI_DEBUG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x20)) | ||
104 | #define BP_EMI_DEBUG_STATIC_STATE 16 | ||
105 | #define BM_EMI_DEBUG_STATIC_STATE 0x70000 | ||
106 | #define BF_EMI_DEBUG_STATIC_STATE(v) (((v) << 16) & 0x70000) | ||
107 | #define BP_EMI_DEBUG_DRAM_STATE 0 | ||
108 | #define BM_EMI_DEBUG_DRAM_STATE 0x1f | ||
109 | #define BF_EMI_DEBUG_DRAM_STATE(v) (((v) << 0) & 0x1f) | ||
110 | |||
111 | /** | ||
112 | * Register: HW_EMI_DRAMSTAT | ||
113 | * Address: 0x80 | ||
114 | * SCT: no | ||
115 | */ | ||
116 | #define HW_EMI_DRAMSTAT (*(volatile unsigned long *)(REGS_EMI_BASE + 0x80)) | ||
117 | #define BP_EMI_DRAMSTAT_SELF_REFRESH_ACK 2 | ||
118 | #define BM_EMI_DRAMSTAT_SELF_REFRESH_ACK 0x4 | ||
119 | #define BF_EMI_DRAMSTAT_SELF_REFRESH_ACK(v) (((v) << 2) & 0x4) | ||
120 | #define BP_EMI_DRAMSTAT_BUSY 1 | ||
121 | #define BM_EMI_DRAMSTAT_BUSY 0x2 | ||
122 | #define BF_EMI_DRAMSTAT_BUSY(v) (((v) << 1) & 0x2) | ||
123 | #define BP_EMI_DRAMSTAT_READY 0 | ||
124 | #define BM_EMI_DRAMSTAT_READY 0x1 | ||
125 | #define BF_EMI_DRAMSTAT_READY(v) (((v) << 0) & 0x1) | ||
126 | |||
127 | /** | ||
128 | * Register: HW_EMI_DRAMCTRL | ||
129 | * Address: 0x90 | ||
130 | * SCT: yes | ||
131 | */ | ||
132 | #define HW_EMI_DRAMCTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x0)) | ||
133 | #define HW_EMI_DRAMCTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x4)) | ||
134 | #define HW_EMI_DRAMCTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0x8)) | ||
135 | #define HW_EMI_DRAMCTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x90 + 0xc)) | ||
136 | #define BP_EMI_DRAMCTRL_EMICLK_DIVIDE 24 | ||
137 | #define BM_EMI_DRAMCTRL_EMICLK_DIVIDE 0x7000000 | ||
138 | #define BF_EMI_DRAMCTRL_EMICLK_DIVIDE(v) (((v) << 24) & 0x7000000) | ||
139 | #define BP_EMI_DRAMCTRL_AUTO_EMICLK_GATE 23 | ||
140 | #define BM_EMI_DRAMCTRL_AUTO_EMICLK_GATE 0x800000 | ||
141 | #define BF_EMI_DRAMCTRL_AUTO_EMICLK_GATE(v) (((v) << 23) & 0x800000) | ||
142 | #define BP_EMI_DRAMCTRL_EMICLK_ENABLE 21 | ||
143 | #define BM_EMI_DRAMCTRL_EMICLK_ENABLE 0x200000 | ||
144 | #define BF_EMI_DRAMCTRL_EMICLK_ENABLE(v) (((v) << 21) & 0x200000) | ||
145 | #define BP_EMI_DRAMCTRL_EMICLKEN_ENABLE 20 | ||
146 | #define BM_EMI_DRAMCTRL_EMICLKEN_ENABLE 0x100000 | ||
147 | #define BF_EMI_DRAMCTRL_EMICLKEN_ENABLE(v) (((v) << 20) & 0x100000) | ||
148 | #define BP_EMI_DRAMCTRL_DRAM_TYPE 16 | ||
149 | #define BM_EMI_DRAMCTRL_DRAM_TYPE 0xf0000 | ||
150 | #define BF_EMI_DRAMCTRL_DRAM_TYPE(v) (((v) << 16) & 0xf0000) | ||
151 | #define BP_EMI_DRAMCTRL_PRECHARGE 2 | ||
152 | #define BM_EMI_DRAMCTRL_PRECHARGE 0x4 | ||
153 | #define BF_EMI_DRAMCTRL_PRECHARGE(v) (((v) << 2) & 0x4) | ||
154 | #define BP_EMI_DRAMCTRL_SELF_REFRESH 1 | ||
155 | #define BM_EMI_DRAMCTRL_SELF_REFRESH 0x2 | ||
156 | #define BF_EMI_DRAMCTRL_SELF_REFRESH(v) (((v) << 1) & 0x2) | ||
157 | |||
158 | /** | ||
159 | * Register: HW_EMI_DRAMADDR | ||
160 | * Address: 0xa0 | ||
161 | * SCT: yes | ||
162 | */ | ||
163 | #define HW_EMI_DRAMADDR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x0)) | ||
164 | #define HW_EMI_DRAMADDR_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x4)) | ||
165 | #define HW_EMI_DRAMADDR_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0x8)) | ||
166 | #define HW_EMI_DRAMADDR_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0xa0 + 0xc)) | ||
167 | #define BP_EMI_DRAMADDR_MODE 8 | ||
168 | #define BM_EMI_DRAMADDR_MODE 0x100 | ||
169 | #define BV_EMI_DRAMADDR_MODE__RBC 0x0 | ||
170 | #define BV_EMI_DRAMADDR_MODE__BRC 0x1 | ||
171 | #define BF_EMI_DRAMADDR_MODE(v) (((v) << 8) & 0x100) | ||
172 | #define BF_EMI_DRAMADDR_MODE_V(v) ((BV_EMI_DRAMADDR_MODE__##v << 8) & 0x100) | ||
173 | #define BP_EMI_DRAMADDR_ROW_BITS 4 | ||
174 | #define BM_EMI_DRAMADDR_ROW_BITS 0xf0 | ||
175 | #define BF_EMI_DRAMADDR_ROW_BITS(v) (((v) << 4) & 0xf0) | ||
176 | #define BP_EMI_DRAMADDR_COLUMN_BITS 0 | ||
177 | #define BM_EMI_DRAMADDR_COLUMN_BITS 0xf | ||
178 | #define BF_EMI_DRAMADDR_COLUMN_BITS(v) (((v) << 0) & 0xf) | ||
179 | |||
180 | /** | ||
181 | * Register: HW_EMI_DRAMMODE | ||
182 | * Address: 0xb0 | ||
183 | * SCT: no | ||
184 | */ | ||
185 | #define HW_EMI_DRAMMODE (*(volatile unsigned long *)(REGS_EMI_BASE + 0xb0)) | ||
186 | #define BP_EMI_DRAMMODE_CAS_LATENCY 4 | ||
187 | #define BM_EMI_DRAMMODE_CAS_LATENCY 0x70 | ||
188 | #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED0 0x0 | ||
189 | #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED1 0x1 | ||
190 | #define BV_EMI_DRAMMODE_CAS_LATENCY__CAS2 0x2 | ||
191 | #define BV_EMI_DRAMMODE_CAS_LATENCY__CAS3 0x3 | ||
192 | #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED4 0x4 | ||
193 | #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED5 0x5 | ||
194 | #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED6 0x6 | ||
195 | #define BV_EMI_DRAMMODE_CAS_LATENCY__RESERVED7 0x7 | ||
196 | #define BF_EMI_DRAMMODE_CAS_LATENCY(v) (((v) << 4) & 0x70) | ||
197 | #define BF_EMI_DRAMMODE_CAS_LATENCY_V(v) ((BV_EMI_DRAMMODE_CAS_LATENCY__##v << 4) & 0x70) | ||
198 | |||
199 | /** | ||
200 | * Register: HW_EMI_DRAMTIME | ||
201 | * Address: 0xc0 | ||
202 | * SCT: yes | ||
203 | */ | ||
204 | #define HW_EMI_DRAMTIME (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x0)) | ||
205 | #define HW_EMI_DRAMTIME_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x4)) | ||
206 | #define HW_EMI_DRAMTIME_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0x8)) | ||
207 | #define HW_EMI_DRAMTIME_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0xc0 + 0xc)) | ||
208 | #define BP_EMI_DRAMTIME_TRFC 24 | ||
209 | #define BM_EMI_DRAMTIME_TRFC 0xf000000 | ||
210 | #define BF_EMI_DRAMTIME_TRFC(v) (((v) << 24) & 0xf000000) | ||
211 | #define BP_EMI_DRAMTIME_TRC 20 | ||
212 | #define BM_EMI_DRAMTIME_TRC 0xf00000 | ||
213 | #define BF_EMI_DRAMTIME_TRC(v) (((v) << 20) & 0xf00000) | ||
214 | #define BP_EMI_DRAMTIME_TRAS 16 | ||
215 | #define BM_EMI_DRAMTIME_TRAS 0xf0000 | ||
216 | #define BF_EMI_DRAMTIME_TRAS(v) (((v) << 16) & 0xf0000) | ||
217 | #define BP_EMI_DRAMTIME_TRCD 12 | ||
218 | #define BM_EMI_DRAMTIME_TRCD 0xf000 | ||
219 | #define BF_EMI_DRAMTIME_TRCD(v) (((v) << 12) & 0xf000) | ||
220 | #define BP_EMI_DRAMTIME_TRP 8 | ||
221 | #define BM_EMI_DRAMTIME_TRP 0x300 | ||
222 | #define BF_EMI_DRAMTIME_TRP(v) (((v) << 8) & 0x300) | ||
223 | #define BP_EMI_DRAMTIME_TXSR 4 | ||
224 | #define BM_EMI_DRAMTIME_TXSR 0xf0 | ||
225 | #define BF_EMI_DRAMTIME_TXSR(v) (((v) << 4) & 0xf0) | ||
226 | #define BP_EMI_DRAMTIME_REFRESH_COUNTER 0 | ||
227 | #define BM_EMI_DRAMTIME_REFRESH_COUNTER 0xf | ||
228 | #define BF_EMI_DRAMTIME_REFRESH_COUNTER(v) (((v) << 0) & 0xf) | ||
229 | |||
230 | /** | ||
231 | * Register: HW_EMI_DRAMTIME2 | ||
232 | * Address: 0xd0 | ||
233 | * SCT: yes | ||
234 | */ | ||
235 | #define HW_EMI_DRAMTIME2 (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x0)) | ||
236 | #define HW_EMI_DRAMTIME2_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x4)) | ||
237 | #define HW_EMI_DRAMTIME2_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0x8)) | ||
238 | #define HW_EMI_DRAMTIME2_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0xd0 + 0xc)) | ||
239 | #define BP_EMI_DRAMTIME2_PRECHARGE_COUNT 0 | ||
240 | #define BM_EMI_DRAMTIME2_PRECHARGE_COUNT 0xffff | ||
241 | #define BF_EMI_DRAMTIME2_PRECHARGE_COUNT(v) (((v) << 0) & 0xffff) | ||
242 | |||
243 | /** | ||
244 | * Register: HW_EMI_STATICCTRL | ||
245 | * Address: 0x100 | ||
246 | * SCT: yes | ||
247 | */ | ||
248 | #define HW_EMI_STATICCTRL (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x0)) | ||
249 | #define HW_EMI_STATICCTRL_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x4)) | ||
250 | #define HW_EMI_STATICCTRL_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0x8)) | ||
251 | #define HW_EMI_STATICCTRL_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x100 + 0xc)) | ||
252 | #define BP_EMI_STATICCTRL_MEM_WIDTH 2 | ||
253 | #define BM_EMI_STATICCTRL_MEM_WIDTH 0x4 | ||
254 | #define BF_EMI_STATICCTRL_MEM_WIDTH(v) (((v) << 2) & 0x4) | ||
255 | #define BP_EMI_STATICCTRL_WRITE_PROTECT 1 | ||
256 | #define BM_EMI_STATICCTRL_WRITE_PROTECT 0x2 | ||
257 | #define BF_EMI_STATICCTRL_WRITE_PROTECT(v) (((v) << 1) & 0x2) | ||
258 | #define BP_EMI_STATICCTRL_RESET_OUT 0 | ||
259 | #define BM_EMI_STATICCTRL_RESET_OUT 0x1 | ||
260 | #define BF_EMI_STATICCTRL_RESET_OUT(v) (((v) << 0) & 0x1) | ||
261 | |||
262 | /** | ||
263 | * Register: HW_EMI_STATICTIME | ||
264 | * Address: 0x110 | ||
265 | * SCT: yes | ||
266 | */ | ||
267 | #define HW_EMI_STATICTIME (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x0)) | ||
268 | #define HW_EMI_STATICTIME_SET (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x4)) | ||
269 | #define HW_EMI_STATICTIME_CLR (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0x8)) | ||
270 | #define HW_EMI_STATICTIME_TOG (*(volatile unsigned long *)(REGS_EMI_BASE + 0x110 + 0xc)) | ||
271 | #define BP_EMI_STATICTIME_THZ 24 | ||
272 | #define BM_EMI_STATICTIME_THZ 0xf000000 | ||
273 | #define BF_EMI_STATICTIME_THZ(v) (((v) << 24) & 0xf000000) | ||
274 | #define BP_EMI_STATICTIME_TDH 16 | ||
275 | #define BM_EMI_STATICTIME_TDH 0xf0000 | ||
276 | #define BF_EMI_STATICTIME_TDH(v) (((v) << 16) & 0xf0000) | ||
277 | #define BP_EMI_STATICTIME_TDS 8 | ||
278 | #define BM_EMI_STATICTIME_TDS 0xf00 | ||
279 | #define BF_EMI_STATICTIME_TDS(v) (((v) << 8) & 0xf00) | ||
280 | #define BP_EMI_STATICTIME_TAS 0 | ||
281 | #define BM_EMI_STATICTIME_TAS 0xf | ||
282 | #define BF_EMI_STATICTIME_TAS(v) (((v) << 0) & 0xf) | ||
283 | |||
284 | #endif /* __HEADERGEN__STMP3600__EMI__H__ */ | ||