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author | Rafaël Carré <rafael.carre@gmail.com> | 2011-12-13 05:13:22 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2011-12-13 05:13:22 +0000 |
commit | c1d789acdb20ae5b7fce737d9ec799a455e791a9 (patch) | |
tree | bb1432039502c10d31085d51054e8e4ea611c3b0 /firmware/target/arm/usb-s3c6400x.c | |
parent | 9c31062f057b40a842fc12c32c22f352f5dea35e (diff) | |
download | rockbox-c1d789acdb20ae5b7fce737d9ec799a455e791a9.tar.gz rockbox-c1d789acdb20ae5b7fce737d9ec799a455e791a9.zip |
usb-s3c6400x.c: use defines instead of hardcoded bitfields
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31222 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/usb-s3c6400x.c')
-rw-r--r-- | firmware/target/arm/usb-s3c6400x.c | 140 |
1 files changed, 69 insertions, 71 deletions
diff --git a/firmware/target/arm/usb-s3c6400x.c b/firmware/target/arm/usb-s3c6400x.c index 4bae6f10f3..ef9fc0d51c 100644 --- a/firmware/target/arm/usb-s3c6400x.c +++ b/firmware/target/arm/usb-s3c6400x.c | |||
@@ -78,32 +78,28 @@ static void reset_endpoints(int reinit) | |||
78 | endpoints[i].done = true; | 78 | endpoints[i].done = true; |
79 | semaphore_release(&endpoints[i].complete); | 79 | semaphore_release(&endpoints[i].complete); |
80 | } | 80 | } |
81 | DIEPCTL(0) = 0x8800; /* EP0 IN ACTIVE NEXT=1 */ | 81 | |
82 | DOEPCTL(0) = 0x8000; /* EP0 OUT ACTIVE */ | 82 | DIEPCTL(0) = DEPCTL_usbactep | (1 << DEPCTL_nextep_bitp); |
83 | DOEPTSIZ(0) = 0x20080040; /* EP0 OUT Transfer Size: | 83 | DOEPCTL(0) = DEPCTL_usbactep; |
84 | 64 Bytes, 1 Packet, 1 Setup Packet */ | 84 | DOEPTSIZ(0) = (1 << DEPTSIZ_pkcnt_bitp) | (1 << DEPTSIZ0_supcnt_bitp) | 64; |
85 | |||
85 | DOEPDMA(0) = &ctrlreq; | 86 | DOEPDMA(0) = &ctrlreq; |
86 | DOEPCTL(0) |= 0x84000000; /* EP0 OUT ENABLE CLEARNAK */ | 87 | DOEPCTL(0) |= DEPCTL_epena | DEPCTL_cnak; |
87 | if (reinit) | 88 | if (reinit) |
88 | { | 89 | { |
89 | /* The size is getting set to zero, because we don't know | 90 | /* The size is getting set to zero, because we don't know |
90 | whether we are Full Speed or High Speed at this stage */ | 91 | whether we are Full Speed or High Speed at this stage */ |
91 | /* EP1 IN INACTIVE DATA0 SIZE=0 NEXT=3 */ | 92 | DIEPCTL(1) = DEPCTL_setd0pid | (3 << DEPCTL_nextep_bitp); |
92 | DIEPCTL(1) = 0x10001800; | 93 | DOEPCTL(2) = DEPCTL_setd0pid; |
93 | /* EP2 OUT INACTIVE DATA0 SIZE=0 */ | 94 | DIEPCTL(3) = DEPCTL_setd0pid | (0 << DEPCTL_nextep_bitp); |
94 | DOEPCTL(2) = 0x10000000; | 95 | DOEPCTL(4) = DEPCTL_setd0pid; |
95 | /* EP3 IN INACTIVE DATA0 SIZE=0 NEXT=0 */ | ||
96 | DIEPCTL(3) = 0x10000000; | ||
97 | /* EP4 OUT INACTIVE DATA0 SIZE=0 */ | ||
98 | DOEPCTL(4) = 0x10000000; | ||
99 | } | 96 | } |
100 | else | 97 | else |
101 | { | 98 | { |
102 | /* INACTIVE DATA0 */ | 99 | DIEPCTL(1) = (DIEPCTL(1) & ~DEPCTL_usbactep) | DEPCTL_setd0pid; |
103 | DIEPCTL(1) = (DIEPCTL(1) & ~0x00008000) | 0x10000000; | 100 | DOEPCTL(2) = (DOEPCTL(2) & ~DEPCTL_usbactep) | DEPCTL_setd0pid; |
104 | DOEPCTL(2) = (DOEPCTL(2) & ~0x00008000) | 0x10000000; | 101 | DIEPCTL(3) = (DIEPCTL(3) & ~DEPCTL_usbactep) | DEPCTL_setd0pid; |
105 | DIEPCTL(3) = (DIEPCTL(3) & ~0x00008000) | 0x10000000; | 102 | DOEPCTL(4) = (DOEPCTL(4) & ~DEPCTL_usbactep) | DEPCTL_setd0pid; |
106 | DOEPCTL(4) = (DOEPCTL(4) & ~0x00008000) | 0x10000000; | ||
107 | } | 103 | } |
108 | DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all EPs */ | 104 | DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all EPs */ |
109 | } | 105 | } |
@@ -122,9 +118,10 @@ int usb_drv_request_endpoint(int type, int dir) | |||
122 | { | 118 | { |
123 | endpoints[ep].active = true; | 119 | endpoints[ep].active = true; |
124 | ret = ep | dir; | 120 | ret = ep | dir; |
125 | uint32_t newbits = (type << 18) | 0x10000000; | 121 | uint32_t newbits = (type << DEPCTL_eptype_bitp) | DEPCTL_epena; |
126 | if (dir) DIEPCTL(ep) = (DIEPCTL(ep) & ~0x000C0000) | newbits; | 122 | uint32_t mask = DEPCTL_eptype_bits << DEPCTL_eptype_bitp; |
127 | else DOEPCTL(ep) = (DOEPCTL(ep) & ~0x000C0000) | newbits; | 123 | if (dir) DIEPCTL(ep) = (DIEPCTL(ep) & ~mask) | newbits; |
124 | else DOEPCTL(ep) = (DOEPCTL(ep) & ~mask) | newbits; | ||
128 | break; | 125 | break; |
129 | } | 126 | } |
130 | ep += 2; | 127 | ep += 2; |
@@ -144,7 +141,7 @@ void usb_drv_release_endpoint(int ep) | |||
144 | 141 | ||
145 | static void usb_reset(void) | 142 | static void usb_reset(void) |
146 | { | 143 | { |
147 | DCTL = 0x802; /* Soft Disconnect */ | 144 | DCTL = DCTL_pwronprgdone | DCTL_sftdiscon; |
148 | 145 | ||
149 | OPHYPWR = 0; /* PHY: Power up */ | 146 | OPHYPWR = 0; /* PHY: Power up */ |
150 | udelay(10); | 147 | udelay(10); |
@@ -157,21 +154,22 @@ static void usb_reset(void) | |||
157 | OPHYCLK = SYNOPSYSOTG_CLOCK; | 154 | OPHYCLK = SYNOPSYSOTG_CLOCK; |
158 | udelay(400); | 155 | udelay(400); |
159 | 156 | ||
160 | GRSTCTL = 1; /* OTG: Assert Software Reset */ | 157 | GRSTCTL = GRSTCTL_csftrst; /* OTG: Assert Software Reset */ |
161 | while (GRSTCTL & 1); /* Wait for OTG to ack reset */ | 158 | while (GRSTCTL & GRSTCTL_csftrst); /* Wait for OTG to ack reset */ |
162 | while (!(GRSTCTL & 0x80000000)); /* Wait for OTG AHB master idle */ | 159 | while (!(GRSTCTL & GRSTCTL_ahbidle)); /* Wait for OTG AHB master idle */ |
160 | |||
161 | GRXFSIZ = 512; | ||
162 | GNPTXFSIZ = MAKE_FIFOSIZE_DATA(512); | ||
163 | 163 | ||
164 | GRXFSIZ = 512; /* RX FIFO: 512 bytes */ | ||
165 | GNPTXFSIZ = MAKE_FIFOSIZE_DATA(512); /* Non-periodic TX FIFO: 512 bytes */ | ||
166 | GAHBCFG = SYNOPSYSOTG_AHBCFG; | 164 | GAHBCFG = SYNOPSYSOTG_AHBCFG; |
167 | GUSBCFG = 0x1408; /* OTG: 16bit PHY and some reserved bits */ | 165 | GUSBCFG = (1 << 12) | (1 << 10) | GUSBCFG_phy_if; /* OTG: 16bit PHY and some reserved bits */ |
168 | 166 | ||
169 | DCFG = 4; /* Address 0 */ | 167 | DCFG = DCFG_nzstsouthshk; /* Address 0 */ |
170 | DCTL = 0x800; /* Soft Reconnect */ | 168 | DCTL = DCTL_pwronprgdone; /* Soft Reconnect */ |
171 | DIEPMSK = 0x0D; /* IN EP interrupt mask */ | 169 | DIEPMSK = DIEPINT_timeout | DIEPINT_ahberr | DIEPINT_xfercompl; |
172 | DOEPMSK = 0x0D; /* IN EP interrupt mask */ | 170 | DOEPMSK = DIEPINT_timeout | DIEPINT_ahberr | DIEPINT_xfercompl; |
173 | DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all endpoints */ | 171 | DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all endpoints */ |
174 | GINTMSK = 0xC3000; /* Interrupt mask: IN event, OUT event, bus reset */ | 172 | GINTMSK = GINTMSK_outepintr | GINTMSK_inepintr | GINTMSK_usbreset | GINTMSK_enumdone; |
175 | 173 | ||
176 | reset_endpoints(1); | 174 | reset_endpoints(1); |
177 | } | 175 | } |
@@ -182,28 +180,28 @@ void INT_USB_FUNC(void) | |||
182 | int i; | 180 | int i; |
183 | uint32_t ints = GINTSTS; | 181 | uint32_t ints = GINTSTS; |
184 | uint32_t epints; | 182 | uint32_t epints; |
185 | if (ints & 0x1000) /* bus reset */ | 183 | if (ints & GINTMSK_usbreset) |
186 | { | 184 | { |
187 | DCFG = 4; /* Address 0 */ | 185 | DCFG = DCFG_nzstsouthshk; /* Address 0 */ |
188 | reset_endpoints(1); | 186 | reset_endpoints(1); |
189 | usb_core_bus_reset(); | 187 | usb_core_bus_reset(); |
190 | } | 188 | } |
191 | 189 | ||
192 | if (ints & 0x2000) /* enumeration done, we now know the speed */ | 190 | if (ints & GINTMSK_enumdone) /* enumeration done, we now know the speed */ |
193 | { | 191 | { |
194 | /* Set up the maximum packet sizes accordingly */ | 192 | /* Set up the maximum packet sizes accordingly */ |
195 | uint32_t maxpacket = usb_drv_port_speed() ? 512 : 64; | 193 | uint32_t maxpacket = (usb_drv_port_speed() ? 512 : 64) << DEPCTL_mps_bitp; |
196 | DIEPCTL(1) = (DIEPCTL(1) & ~0x000003FF) | maxpacket; | 194 | DIEPCTL(1) = (DIEPCTL(1) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket; |
197 | DOEPCTL(2) = (DOEPCTL(2) & ~0x000003FF) | maxpacket; | 195 | DOEPCTL(2) = (DOEPCTL(2) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket; |
198 | DIEPCTL(3) = (DIEPCTL(3) & ~0x000003FF) | maxpacket; | 196 | DIEPCTL(3) = (DIEPCTL(3) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket; |
199 | DOEPCTL(4) = (DOEPCTL(4) & ~0x000003FF) | maxpacket; | 197 | DOEPCTL(4) = (DOEPCTL(4) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket; |
200 | } | 198 | } |
201 | 199 | ||
202 | if (ints & 0x40000) /* IN EP event */ | 200 | if (ints & GINTMSK_inepintr) |
203 | for (i = 0; i < 4; i += i + 1) // 0, 1, 3 | 201 | for (i = 0; i < 4; i += i + 1) // 0, 1, 3 |
204 | if ((epints = DIEPINT(i))) | 202 | if ((epints = DIEPINT(i))) |
205 | { | 203 | { |
206 | if (epints & 1) /* Transfer completed */ | 204 | if (epints & DIEPINT_xfercompl) |
207 | { | 205 | { |
208 | invalidate_dcache(); | 206 | invalidate_dcache(); |
209 | int bytes = endpoints[i].size - (DIEPTSIZ(i) & 0x3FFFF); | 207 | int bytes = endpoints[i].size - (DIEPTSIZ(i) & 0x3FFFF); |
@@ -216,9 +214,9 @@ void INT_USB_FUNC(void) | |||
216 | semaphore_release(&endpoints[i].complete); | 214 | semaphore_release(&endpoints[i].complete); |
217 | } | 215 | } |
218 | } | 216 | } |
219 | if (epints & 4) /* AHB error */ | 217 | if (epints & DIEPINT_ahberr) |
220 | panicf("USB: AHB error on IN EP%d", i); | 218 | panicf("USB: AHB error on IN EP%d", i); |
221 | if (epints & 8) /* Timeout */ | 219 | if (epints & DIEPINT_timeout) |
222 | { | 220 | { |
223 | if (endpoints[i].busy) | 221 | if (endpoints[i].busy) |
224 | { | 222 | { |
@@ -231,14 +229,14 @@ void INT_USB_FUNC(void) | |||
231 | DIEPINT(i) = epints; | 229 | DIEPINT(i) = epints; |
232 | } | 230 | } |
233 | 231 | ||
234 | if (ints & 0x80000) /* OUT EP event */ | 232 | if (ints & GINTMSK_outepintr) |
235 | for (i = 0; i < USB_NUM_ENDPOINTS; i += 2) | 233 | for (i = 0; i < USB_NUM_ENDPOINTS; i += 2) |
236 | if ((epints = DOEPINT(i))) | 234 | if ((epints = DOEPINT(i))) |
237 | { | 235 | { |
238 | if (epints & 1) /* Transfer completed */ | 236 | if (epints & DIEPINT_xfercompl) |
239 | { | 237 | { |
240 | invalidate_dcache(); | 238 | invalidate_dcache(); |
241 | int bytes = endpoints[i].size - (DOEPTSIZ(i) & 0x3FFFF); | 239 | int bytes = endpoints[i].size - (DOEPTSIZ(i) & (DEPTSIZ_xfersize_bits < DEPTSIZ_xfersize_bitp)); |
242 | if (endpoints[i].busy) | 240 | if (endpoints[i].busy) |
243 | { | 241 | { |
244 | endpoints[i].busy = false; | 242 | endpoints[i].busy = false; |
@@ -248,9 +246,9 @@ void INT_USB_FUNC(void) | |||
248 | semaphore_release(&endpoints[i].complete); | 246 | semaphore_release(&endpoints[i].complete); |
249 | } | 247 | } |
250 | } | 248 | } |
251 | if (epints & 4) /* AHB error */ | 249 | if (epints & DIEPINT_ahberr) |
252 | panicf("USB: AHB error on OUT EP%d", i); | 250 | panicf("USB: AHB error on OUT EP%d", i); |
253 | if (epints & 8) /* SETUP phase done */ | 251 | if (epints & DIEPINT_timeout) /* SETUP phase done */ |
254 | { | 252 | { |
255 | invalidate_dcache(); | 253 | invalidate_dcache(); |
256 | if (i == 0) | 254 | if (i == 0) |
@@ -260,18 +258,18 @@ void INT_USB_FUNC(void) | |||
260 | /* Already set the new address here, | 258 | /* Already set the new address here, |
261 | before passing the packet to the core. | 259 | before passing the packet to the core. |
262 | See below (usb_drv_set_address) for details. */ | 260 | See below (usb_drv_set_address) for details. */ |
263 | DCFG = (DCFG & ~0x7F0) | (ctrlreq.header.wValue << 4); | 261 | DCFG = (DCFG & ~(DCFG_devadr_bits << DCFG_devadr_bitp)) | (ctrlreq.header.wValue << DCFG_devadr_bitp); |
264 | } | 262 | } |
265 | usb_core_control_request(&ctrlreq.header); | 263 | usb_core_control_request(&ctrlreq.header); |
266 | } | 264 | } |
267 | else panicf("USB: SETUP done on OUT EP%d!?", i); | 265 | else panicf("USB: SETUP done on OUT EP%d!?", i); |
268 | } | 266 | } |
269 | /* Make sure EP0 OUT is set up to accept the next request */ | 267 | /* Make sure EP0 OUT is set up to accept the next request */ |
270 | if (!i) | 268 | if (i == 0) |
271 | { | 269 | { |
272 | DOEPTSIZ(0) = 0x20080040; | 270 | DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bitp) | (1 << DEPTSIZ0_pkcnt_bitp) | 64; |
273 | DOEPDMA(0) = &ctrlreq; | 271 | DOEPDMA(0) = &ctrlreq; |
274 | DOEPCTL(0) |= 0x84000000; | 272 | DOEPCTL(0) |= DEPCTL_epena | DEPCTL_cnak; |
275 | } | 273 | } |
276 | DOEPINT(i) = epints; | 274 | DOEPINT(i) = epints; |
277 | } | 275 | } |
@@ -292,43 +290,43 @@ static void ep_send(int ep, const void *ptr, int length) | |||
292 | { | 290 | { |
293 | endpoints[ep].busy = true; | 291 | endpoints[ep].busy = true; |
294 | endpoints[ep].size = length; | 292 | endpoints[ep].size = length; |
295 | DIEPCTL(ep) |= 0x8000; /* EPx OUT ACTIVE */ | 293 | DIEPCTL(ep) |= DEPCTL_usbactep; |
296 | int blocksize = usb_drv_port_speed() ? 512 : 64; | 294 | int blocksize = usb_drv_port_speed() ? 512 : 64; |
297 | int packets = (length + blocksize - 1) / blocksize; | 295 | int packets = (length + blocksize - 1) / blocksize; |
298 | if (!length) | 296 | if (!length) |
299 | { | 297 | { |
300 | DIEPTSIZ(ep) = 1 << 19; /* one empty packet */ | 298 | DIEPTSIZ(ep) = 1 << DEPTSIZ0_pkcnt_bitp; /* one empty packet */ |
301 | DIEPDMA(ep) = NULL; | 299 | DIEPDMA(ep) = NULL; |
302 | } | 300 | } |
303 | else | 301 | else |
304 | { | 302 | { |
305 | DIEPTSIZ(ep) = length | (packets << 19); | 303 | DIEPTSIZ(ep) = length | (packets << DEPTSIZ0_pkcnt_bitp); |
306 | DIEPDMA(ep) = ptr; | 304 | DIEPDMA(ep) = ptr; |
307 | } | 305 | } |
308 | clean_dcache(); | 306 | clean_dcache(); |
309 | DIEPCTL(ep) |= 0x84000000; /* EPx OUT ENABLE CLEARNAK */ | 307 | DIEPCTL(ep) |= DEPCTL_epena | DEPCTL_cnak; |
310 | } | 308 | } |
311 | 309 | ||
312 | static void ep_recv(int ep, void *ptr, int length) | 310 | static void ep_recv(int ep, void *ptr, int length) |
313 | { | 311 | { |
314 | endpoints[ep].busy = true; | 312 | endpoints[ep].busy = true; |
315 | endpoints[ep].size = length; | 313 | endpoints[ep].size = length; |
316 | DOEPCTL(ep) &= ~0x20000; /* EPx UNSTALL */ | 314 | DOEPCTL(ep) &= ~DEPCTL_naksts; |
317 | DOEPCTL(ep) |= 0x8000; /* EPx OUT ACTIVE */ | 315 | DOEPCTL(ep) |= DEPCTL_usbactep; |
318 | int blocksize = usb_drv_port_speed() ? 512 : 64; | 316 | int blocksize = usb_drv_port_speed() ? 512 : 64; |
319 | int packets = (length + blocksize - 1) / blocksize; | 317 | int packets = (length + blocksize - 1) / blocksize; |
320 | if (!length) | 318 | if (!length) |
321 | { | 319 | { |
322 | DOEPTSIZ(ep) = 1 << 19; /* one empty packet */ | 320 | DOEPTSIZ(ep) = 1 << DEPTSIZ0_pkcnt_bitp; /* one empty packet */ |
323 | DOEPDMA(ep) = NULL; | 321 | DOEPDMA(ep) = NULL; |
324 | } | 322 | } |
325 | else | 323 | else |
326 | { | 324 | { |
327 | DOEPTSIZ(ep) = length | (packets << 19); | 325 | DOEPTSIZ(ep) = length | (packets << DEPTSIZ0_pkcnt_bitp); |
328 | DOEPDMA(ep) = ptr; | 326 | DOEPDMA(ep) = ptr; |
329 | } | 327 | } |
330 | clean_dcache(); | 328 | clean_dcache(); |
331 | DOEPCTL(ep) |= 0x84000000; /* EPx OUT ENABLE CLEARNAK */ | 329 | DOEPCTL(ep) |= DEPCTL_epena | DEPCTL_cnak; |
332 | } | 330 | } |
333 | 331 | ||
334 | int usb_drv_send(int endpoint, void *ptr, int length) | 332 | int usb_drv_send(int endpoint, void *ptr, int length) |
@@ -367,21 +365,21 @@ void usb_drv_set_test_mode(int mode) | |||
367 | 365 | ||
368 | bool usb_drv_stalled(int endpoint, bool in) | 366 | bool usb_drv_stalled(int endpoint, bool in) |
369 | { | 367 | { |
370 | if (in) return DIEPCTL(endpoint) & 0x00200000 ? true : false; | 368 | if (in) return DIEPCTL(endpoint) & DEPCTL_naksts; |
371 | else return DOEPCTL(endpoint) & 0x00200000 ? true : false; | 369 | else return DOEPCTL(endpoint) & DEPCTL_naksts; |
372 | } | 370 | } |
373 | 371 | ||
374 | void usb_drv_stall(int endpoint, bool stall, bool in) | 372 | void usb_drv_stall(int endpoint, bool stall, bool in) |
375 | { | 373 | { |
376 | if (in) | 374 | if (in) |
377 | { | 375 | { |
378 | if (stall) DIEPCTL(endpoint) |= 0x00200000; | 376 | if (stall) DIEPCTL(endpoint) |= DEPCTL_naksts; |
379 | else DIEPCTL(endpoint) &= ~0x00200000; | 377 | else DIEPCTL(endpoint) &= ~DEPCTL_naksts; |
380 | } | 378 | } |
381 | else | 379 | else |
382 | { | 380 | { |
383 | if (stall) DOEPCTL(endpoint) |= 0x00200000; | 381 | if (stall) DOEPCTL(endpoint) |= DEPCTL_naksts; |
384 | else DOEPCTL(endpoint) &= ~0x00200000; | 382 | else DOEPCTL(endpoint) &= ~DEPCTL_naksts; |
385 | } | 383 | } |
386 | } | 384 | } |
387 | 385 | ||
@@ -405,7 +403,7 @@ void usb_drv_init(void) | |||
405 | 403 | ||
406 | void usb_drv_exit(void) | 404 | void usb_drv_exit(void) |
407 | { | 405 | { |
408 | DCTL = 0x802; /* Soft Disconnect */ | 406 | DCTL = DCTL_pwronprgdone | DCTL_sftdiscon; |
409 | 407 | ||
410 | OPHYPWR = 0xF; /* PHY: Power down */ | 408 | OPHYPWR = 0xF; /* PHY: Power down */ |
411 | udelay(10); | 409 | udelay(10); |
@@ -465,7 +463,7 @@ int usb_detect(void) | |||
465 | #else | 463 | #else |
466 | void usb_init_device(void) | 464 | void usb_init_device(void) |
467 | { | 465 | { |
468 | DCTL = 0x802; /* Soft Disconnect */ | 466 | DCTL = DCTL_pwronprgdone | DCTL_sftdiscon; |
469 | 467 | ||
470 | ORSTCON = 1; /* Put the PHY into reset (needed to get current down) */ | 468 | ORSTCON = 1; /* Put the PHY into reset (needed to get current down) */ |
471 | PCGCCTL = 1; /* Shut down PHY clock */ | 469 | PCGCCTL = 1; /* Shut down PHY clock */ |