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author | Tomasz Moń <desowin@gmail.com> | 2011-12-21 16:06:36 +0000 |
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committer | Tomasz Moń <desowin@gmail.com> | 2011-12-21 16:06:36 +0000 |
commit | 2800c55a6adda5987d9675e3e73185b8d7b30cab (patch) | |
tree | 90e1b6c40add3eaf33e8c1693486dae9ada52d34 /firmware/target/arm/tms320dm320/system-dm320.c | |
parent | 2c85013434852540695bfbb74915a023d0e252ab (diff) | |
download | rockbox-2800c55a6adda5987d9675e3e73185b8d7b30cab.tar.gz rockbox-2800c55a6adda5987d9675e3e73185b8d7b30cab.zip |
TMS320DM320: Check for TIMER1 bit in udelay().
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31394 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tms320dm320/system-dm320.c')
-rw-r--r-- | firmware/target/arm/tms320dm320/system-dm320.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c index 741516a950..12e0b6d03d 100644 --- a/firmware/target/arm/tms320dm320/system-dm320.c +++ b/firmware/target/arm/tms320dm320/system-dm320.c | |||
@@ -437,7 +437,7 @@ void udelay(int usec) { | |||
437 | 437 | ||
438 | /* | 438 | /* |
439 | * Status in IO_INTC_IRQ0 is changed even when interrupts are | 439 | * Status in IO_INTC_IRQ0 is changed even when interrupts are |
440 | * masked. If IRQ_TIMER1 bit in IO_INTC_IRQ0 is set to 0, then | 440 | * masked. If bit 1 in IO_INTC_IRQ0 is set to 0, then |
441 | * there is pending current_tick update. | 441 | * there is pending current_tick update. |
442 | * | 442 | * |
443 | * Relaying solely on current_tick value when interrupts are disabled | 443 | * Relaying solely on current_tick value when interrupts are disabled |
@@ -450,13 +450,13 @@ void udelay(int usec) { | |||
450 | /* udelay will end after counter reset (tick) */ | 450 | /* udelay will end after counter reset (tick) */ |
451 | while ((IO_TIMER1_TMCNT < stop) || | 451 | while ((IO_TIMER1_TMCNT < stop) || |
452 | ((current_tick == prev_tick) /* ensure new tick */ && | 452 | ((current_tick == prev_tick) /* ensure new tick */ && |
453 | (IO_INTC_IRQ0 & IRQ_TIMER1))); /* prevent lock */ | 453 | (IO_INTC_IRQ0 & (1 << 1)))); /* prevent lock */ |
454 | } | 454 | } |
455 | else | 455 | else |
456 | { | 456 | { |
457 | /* udelay will end before counter reset (tick) */ | 457 | /* udelay will end before counter reset (tick) */ |
458 | while ((IO_TIMER1_TMCNT < stop) && | 458 | while ((IO_TIMER1_TMCNT < stop) && |
459 | ((current_tick == prev_tick) && (IO_INTC_IRQ0 & IRQ_TIMER1))); | 459 | ((current_tick == prev_tick) && (IO_INTC_IRQ0 & (1 << 1)))); |
460 | } | 460 | } |
461 | } | 461 | } |
462 | 462 | ||