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authorKarl Kurbjun <kkurbjun@gmail.com>2007-10-26 05:17:15 +0000
committerKarl Kurbjun <kkurbjun@gmail.com>2007-10-26 05:17:15 +0000
commit0a632680e9785f60bc0dd0504d188210d58d2f83 (patch)
treebffe8479c511194ecdf36dfee02fd3328a038809 /firmware/target/arm/tms320dm320/system-dm320.c
parentcf86a9886f689f325dc2d7beec23c74366bdc9af (diff)
downloadrockbox-0a632680e9785f60bc0dd0504d188210d58d2f83.tar.gz
rockbox-0a632680e9785f60bc0dd0504d188210d58d2f83.zip
Some small cleanups and code for testing
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@15312 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tms320dm320/system-dm320.c')
-rw-r--r--firmware/target/arm/tms320dm320/system-dm320.c20
1 files changed, 9 insertions, 11 deletions
diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c
index f3f8dcea26..c009766f21 100644
--- a/firmware/target/arm/tms320dm320/system-dm320.c
+++ b/firmware/target/arm/tms320dm320/system-dm320.c
@@ -22,6 +22,7 @@
22#include "system.h" 22#include "system.h"
23#include "panic.h" 23#include "panic.h"
24#include "uart-target.h" 24#include "uart-target.h"
25#include "system-arm.h"
25#include "spi.h" 26#include "spi.h"
26 27
27#define default_interrupt(name) \ 28#define default_interrupt(name) \
@@ -143,11 +144,6 @@ void system_reboot(void)
143 144
144} 145}
145 146
146void enable_interrupts (void)
147{
148 asm volatile ("msr cpsr_c, #0x13" );
149}
150
151void system_init(void) 147void system_init(void)
152{ 148{
153 /* taken from linux/arch/arm/mach-itdm320-20/irq.c */ 149 /* taken from linux/arch/arm/mach-itdm320-20/irq.c */
@@ -171,22 +167,24 @@ void system_init(void)
171 IO_INTC_FISEL1 = 0; 167 IO_INTC_FISEL1 = 0;
172 IO_INTC_FISEL2 = 0; 168 IO_INTC_FISEL2 = 0;
173 169
174 IO_INTC_ENTRY_TBA0 = 170 IO_INTC_ENTRY_TBA0 = 0;
175 IO_INTC_ENTRY_TBA1 = 0; 171 IO_INTC_ENTRY_TBA1 = 0;
176 172
177 /* set GIO26 (reset pin) to output and low */ 173 /* set GIO26 (reset pin) to output and low */
178 IO_GIO_BITCLR1=(1<<10); 174 IO_GIO_BITCLR1=(1<<10);
179 IO_GIO_DIR1&=~(1<<10); 175 IO_GIO_DIR1&=~(1<<10);
180 176
181 enable_interrupts();
182 uart_init(); 177 uart_init();
183 spi_init(); 178 spi_init();
184 179
185 /* MMU initialization (Starts data and instruction cache) */ 180 /* MMU initialization (Starts data and instruction cache) */
186 ttb_init(); 181 ttb_init();
187 map_section(0, 0, 0x1000, CACHE_NONE); /* Make sure everything is mapped on itself */ 182 /* Make sure everything is mapped on itself */
188 map_section(0x00900000, 0x00900000, 64, CACHE_ALL); /* Enable caching for RAM */ 183 map_section(0, 0, 0x1000, CACHE_NONE);
189 map_section((int)FRAME, (int)FRAME, 2, BUFFERED); /* enable buffered writing for the framebuffer */ 184 /* Enable caching for RAM */
185 map_section(0x00900000, 0x00900000, 64, CACHE_ALL);
186 /* enable buffered writing for the framebuffer */
187 map_section((int)FRAME, (int)FRAME, 1, BUFFERED);
190 enable_mmu(); 188 enable_mmu();
191} 189}
192 190