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author | Michael Sevakis <jethead71@rockbox.org> | 2008-01-18 13:12:33 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2008-01-18 13:12:33 +0000 |
commit | 6a8379674c43103c008f841968b84287b8fdaf89 (patch) | |
tree | 39003a711cfff5cdf5ad00a56c70ae34f34d5100 /firmware/target/arm/tms320dm320/spi-dm320.c | |
parent | 3b36b98ff8dea187bd6c25174978da4f7b5e3231 (diff) | |
download | rockbox-6a8379674c43103c008f841968b84287b8fdaf89.tar.gz rockbox-6a8379674c43103c008f841968b84287b8fdaf89.zip |
Finally, out goes struct spinlock for anything but mutiprocessor targets where it becomes a reenterable corelock.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16105 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tms320dm320/spi-dm320.c')
-rw-r--r-- | firmware/target/arm/tms320dm320/spi-dm320.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/target/arm/tms320dm320/spi-dm320.c b/firmware/target/arm/tms320dm320/spi-dm320.c index f3b41add54..d8f338f592 100644 --- a/firmware/target/arm/tms320dm320/spi-dm320.c +++ b/firmware/target/arm/tms320dm320/spi-dm320.c | |||
@@ -32,7 +32,7 @@ | |||
32 | #define GIO_RTC_ENABLE (1<<12) | 32 | #define GIO_RTC_ENABLE (1<<12) |
33 | #define GIO_BL_ENABLE (1<<13) | 33 | #define GIO_BL_ENABLE (1<<13) |
34 | 34 | ||
35 | struct spinlock spi_lock; | 35 | struct mutex spi_mtx; |
36 | 36 | ||
37 | struct SPI_info { | 37 | struct SPI_info { |
38 | volatile unsigned short *setreg; | 38 | volatile unsigned short *setreg; |
@@ -60,7 +60,7 @@ int spi_block_transfer(enum SPI_target target, | |||
60 | const uint8_t *tx_bytes, unsigned int tx_size, | 60 | const uint8_t *tx_bytes, unsigned int tx_size, |
61 | uint8_t *rx_bytes, unsigned int rx_size) | 61 | uint8_t *rx_bytes, unsigned int rx_size) |
62 | { | 62 | { |
63 | spinlock_lock(&spi_lock); | 63 | mutex_lock(&spi_mtx); |
64 | /* Activate the slave select pin */ | 64 | /* Activate the slave select pin */ |
65 | *spi_targets[target].setreg = spi_targets[target].bit; | 65 | *spi_targets[target].setreg = spi_targets[target].bit; |
66 | 66 | ||
@@ -87,13 +87,13 @@ int spi_block_transfer(enum SPI_target target, | |||
87 | 87 | ||
88 | *spi_targets[target].clrreg = spi_targets[target].bit; | 88 | *spi_targets[target].clrreg = spi_targets[target].bit; |
89 | 89 | ||
90 | spinlock_unlock(&spi_lock); | 90 | mutex_unlock(&spi_mtx); |
91 | return 0; | 91 | return 0; |
92 | } | 92 | } |
93 | 93 | ||
94 | void spi_init(void) | 94 | void spi_init(void) |
95 | { | 95 | { |
96 | spinlock_init(&spi_lock); | 96 | mutex_init(&spi_mtx); |
97 | /* Set SCLK idle level = 0 */ | 97 | /* Set SCLK idle level = 0 */ |
98 | IO_SERIAL0_MODE |= 1<<10; | 98 | IO_SERIAL0_MODE |= 1<<10; |
99 | /* Enable TX */ | 99 | /* Enable TX */ |