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authorJonathan Gordon <rockbox@jdgordon.info>2007-09-30 08:57:49 +0000
committerJonathan Gordon <rockbox@jdgordon.info>2007-09-30 08:57:49 +0000
commit80f1688423eaad7a2ad9e4809331e192bcd0047d (patch)
tree716c8e3160daaa7f462cfe6cf6f848c41b61b2e6 /firmware/target/arm/tms320dm320/mrobe-500/ata-mr500.c
parenta5e788fe8533f6172b3d6b52d2430fe163f7a6fd (diff)
downloadrockbox-80f1688423eaad7a2ad9e4809331e192bcd0047d.tar.gz
rockbox-80f1688423eaad7a2ad9e4809331e192bcd0047d.zip
I got bullied in IRC by linuxstb and markun...
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14909 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tms320dm320/mrobe-500/ata-mr500.c')
-rw-r--r--firmware/target/arm/tms320dm320/mrobe-500/ata-mr500.c131
1 files changed, 131 insertions, 0 deletions
diff --git a/firmware/target/arm/tms320dm320/mrobe-500/ata-mr500.c b/firmware/target/arm/tms320dm320/mrobe-500/ata-mr500.c
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index 0000000000..47a8c61a45
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+++ b/firmware/target/arm/tms320dm320/mrobe-500/ata-mr500.c
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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2007 by Karl Kurbjun
11 *
12 * All files in this archive are subject to the GNU General Public License.
13 * See the file COPYING in the source tree root for full license agreement.
14 *
15 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16 * KIND, either express or implied.
17 *
18 ****************************************************************************/
19
20#include "config.h"
21#include "cpu.h"
22#include "kernel.h"
23#include "thread.h"
24#include "system.h"
25#include "power.h"
26#include "panic.h"
27#include "pcf50606.h"
28#include "ata-target.h"
29#include "backlight-target.h"
30
31/* ARESET on C7C68300 and RESET on ATA interface (Active Low) */
32#define ATA_RESET_ENABLE (IO_GIO_BITCLR0 = 1 << 10)
33#define ATA_RESET_DISABLE (IO_GIO_BITSET0 = 1 << 10)
34
35/* ATA_EN on C7C68300 */
36#define USB_ATA_ENABLE (IO_GIO_BITSET0 = 1 << 2)
37#define USB_ATA_DISABLE (IO_GIO_BITCLR0 = 1 << 2)
38
39void ata_reset(void)
40{
41 ATA_RESET_ENABLE;
42 sleep(1); /* > 25us */
43 ATA_RESET_DISABLE;
44 sleep(1); /* > 2ms */
45}
46
47/* This function is called before enabling the USB bus */
48void ata_enable(bool on)
49{
50 if(on)
51 USB_ATA_DISABLE;
52 else
53 USB_ATA_ENABLE;
54}
55
56bool ata_is_coldstart(void)
57{
58 return true;
59}
60
61void ata_device_init(void)
62{
63 /* ATA reset */
64 ATA_RESET_DISABLE; /* Set the pin to disable an active low reset */
65 IO_GIO_DIR0&=~(1<<10);
66}
67
68#if 0
69void copy_read_sectors(unsigned char* buf, int wordcount)
70{
71 __buttonlight_trigger();
72
73 /* Unaligned transfer - slow copy */
74 if ( (unsigned long)buf & 1)
75 { /* not 16-bit aligned, copy byte by byte */
76 unsigned short tmp = 0;
77 unsigned char* bufend = buf + wordcount*2;
78 do
79 {
80 tmp = ATA_DATA;
81 *buf++ = tmp & 0xff; /* I assume big endian */
82 *buf++ = tmp >> 8; /* and don't use the SWAB16 macro */
83 } while (buf < bufend); /* tail loop is faster */
84 return;
85 }
86 /* This should never happen, but worth watching for */
87 if(wordcount > (1 << 18))
88 panicf("atd-meg-fx.c: copy_read_sectors: too many sectors per read!");
89
90//#define GIGABEAT_DEBUG_ATA
91#ifdef GIGABEAT_DEBUG_ATA
92 static int line = 0;
93 static char str[256];
94 snprintf(str, sizeof(str), "ODD DMA to %08x, %d", buf, wordcount);
95 lcd_puts(10, line, str);
96 line = (line+1) % 32;
97 lcd_update();
98#endif
99 /* Reset the channel */
100 DMASKTRIG0 |= 4;
101 /* Wait for DMA controller to be ready */
102 while(DMASKTRIG0 & 0x2)
103 ;
104 while(DSTAT0 & (1 << 20))
105 ;
106 /* Source is ATA_DATA, on AHB Bus, Fixed */
107 DISRC0 = (int) 0x18000000;
108 DISRCC0 = 0x1;
109 /* Dest mapped to physical address, on AHB bus, increment */
110 DIDST0 = (int) buf;
111 if(DIDST0 < 0x30000000)
112 DIDST0 += 0x30000000;
113 DIDSTC0 = 0;
114
115 /* DACK/DREQ Sync to AHB, Whole service, No reload, 16-bit transfers */
116 DCON0 = ((1 << 30) | (1<<27) | (1<<22) | (1<<20)) | wordcount;
117
118 /* Activate the channel */
119 DMASKTRIG0 = 0x2;
120
121 invalidate_dcache_range((void *)buf, wordcount*2);
122
123 /* Start DMA */
124 DMASKTRIG0 |= 0x1;
125
126 /* Wait for transfer to complete */
127 while((DSTAT0 & 0x000fffff))
128 priority_yield();
129 /* Dump cache for the buffer */
130}
131#endif