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author | Rafaël Carré <rafael.carre@gmail.com> | 2008-11-26 15:38:10 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2008-11-26 15:38:10 +0000 |
commit | aaaf609996bf8e5c651fcf3aa20399a27f953cbc (patch) | |
tree | a8d240b1941813fabaadd3463c4a755dbf395949 /firmware/target/arm/tms320dm320/creative-zvm/dma-creativezvm.c | |
parent | 888c3477bb09fefb68228cf54875ec0b359ee710 (diff) | |
download | rockbox-aaaf609996bf8e5c651fcf3aa20399a27f953cbc.tar.gz rockbox-aaaf609996bf8e5c651fcf3aa20399a27f953cbc.zip |
Creative ZVM : cosmetics
Use only UNIX line endings, remove trailing whitespace
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19232 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tms320dm320/creative-zvm/dma-creativezvm.c')
-rw-r--r-- | firmware/target/arm/tms320dm320/creative-zvm/dma-creativezvm.c | 252 |
1 files changed, 126 insertions, 126 deletions
diff --git a/firmware/target/arm/tms320dm320/creative-zvm/dma-creativezvm.c b/firmware/target/arm/tms320dm320/creative-zvm/dma-creativezvm.c index 201dd1b24c..c229b9957a 100644 --- a/firmware/target/arm/tms320dm320/creative-zvm/dma-creativezvm.c +++ b/firmware/target/arm/tms320dm320/creative-zvm/dma-creativezvm.c | |||
@@ -1,130 +1,130 @@ | |||
1 | /*************************************************************************** | 1 | /*************************************************************************** |
2 | * __________ __ ___. | 2 | * __________ __ ___. |
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | 3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ |
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | 4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / |
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | 5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < |
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | 6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ |
7 | * \/ \/ \/ \/ \/ | 7 | * \/ \/ \/ \/ \/ |
8 | * $Id$ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2008 by Maurus Cuelenaere | 10 | * Copyright (C) 2008 by Maurus Cuelenaere |
11 | * | 11 | * |
12 | * This program is free software; you can redistribute it and/or | 12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 13 | * modify it under the terms of the GNU General Public License |
14 | * as published by the Free Software Foundation; either version 2 | 14 | * as published by the Free Software Foundation; either version 2 |
15 | * of the License, or (at your option) any later version. | 15 | * of the License, or (at your option) any later version. |
16 | * | 16 | * |
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | 17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY |
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "kernel.h" | 23 | #include "kernel.h" |
24 | #include "thread.h" | 24 | #include "thread.h" |
25 | #include "system.h" | 25 | #include "system.h" |
26 | #include "dma-target.h" | 26 | #include "dma-target.h" |
27 | #include "dm320.h" | 27 | #include "dm320.h" |
28 | #include "ata-target.h" | 28 | #include "ata-target.h" |
29 | #include <stdbool.h> | 29 | #include <stdbool.h> |
30 | 30 | ||
31 | #define CS1_START 0x50000000 | 31 | #define CS1_START 0x50000000 |
32 | #define CS2_START 0x60000000 | 32 | #define CS2_START 0x60000000 |
33 | #define SDRAM_START 0x00900000 | 33 | #define SDRAM_START 0x00900000 |
34 | #define FLASH_START 0x00100000 | 34 | #define FLASH_START 0x00100000 |
35 | #define CF_START 0x40000000 | 35 | #define CF_START 0x40000000 |
36 | #define SSFDC_START 0x48000000 | 36 | #define SSFDC_START 0x48000000 |
37 | 37 | ||
38 | static struct wakeup transfer_completion_signal; | 38 | static struct wakeup transfer_completion_signal; |
39 | 39 | ||
40 | static bool dma_in_progress = false; | 40 | static bool dma_in_progress = false; |
41 | 41 | ||
42 | void MTC0(void) | 42 | void MTC0(void) |
43 | { | 43 | { |
44 | IO_INTC_IRQ1 = INTR_IRQ1_MTC0; | 44 | IO_INTC_IRQ1 = INTR_IRQ1_MTC0; |
45 | wakeup_signal(&transfer_completion_signal); | 45 | wakeup_signal(&transfer_completion_signal); |
46 | dma_in_progress = false; | 46 | dma_in_progress = false; |
47 | } | 47 | } |
48 | 48 | ||
49 | void dma_start(const void* addr, size_t size) | 49 | void dma_start(const void* addr, size_t size) |
50 | { | 50 | { |
51 | /* Compatibility with Gigabeat S in dma_start.c */ | 51 | /* Compatibility with Gigabeat S in dma_start.c */ |
52 | (void) addr; | 52 | (void) addr; |
53 | (void) size; | 53 | (void) size; |
54 | } | 54 | } |
55 | 55 | ||
56 | #define ATA_DEST (ATA_IOBASE-CS1_START) | 56 | #define ATA_DEST (ATA_IOBASE-CS1_START) |
57 | void dma_ata_read(unsigned char* buf, int shortcount) | 57 | void dma_ata_read(unsigned char* buf, int shortcount) |
58 | { | 58 | { |
59 | if(dma_in_progress) | 59 | if(dma_in_progress) |
60 | wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); | 60 | wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); |
61 | 61 | ||
62 | while((unsigned long)buf & 0x1F) | 62 | while((unsigned long)buf & 0x1F) |
63 | { | 63 | { |
64 | unsigned short tmp; | 64 | unsigned short tmp; |
65 | tmp = ATA_DATA; | 65 | tmp = ATA_DATA; |
66 | *buf++ = tmp & 0xFF; | 66 | *buf++ = tmp & 0xFF; |
67 | *buf++ = tmp >> 8; | 67 | *buf++ = tmp >> 8; |
68 | shortcount--; | 68 | shortcount--; |
69 | } | 69 | } |
70 | 70 | ||
71 | if (!shortcount) | 71 | if (!shortcount) |
72 | return; | 72 | return; |
73 | 73 | ||
74 | IO_SDRAM_SDDMASEL = 0x0820; /* 32-byte burst mode transfer */ | 74 | IO_SDRAM_SDDMASEL = 0x0820; /* 32-byte burst mode transfer */ |
75 | IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */ | 75 | IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */ |
76 | IO_EMIF_AHBADDH = ((unsigned long)buf >> 16) & 0x7FFF; /* Set variable address */ | 76 | IO_EMIF_AHBADDH = ((unsigned long)buf >> 16) & 0x7FFF; /* Set variable address */ |
77 | IO_EMIF_AHBADDL = (unsigned long)buf & 0xFFFF; | 77 | IO_EMIF_AHBADDL = (unsigned long)buf & 0xFFFF; |
78 | IO_EMIF_MTCADDH = ( (1 << 15) | (ATA_DEST >> 16) ); /* Set fixed address */ | 78 | IO_EMIF_MTCADDH = ( (1 << 15) | (ATA_DEST >> 16) ); /* Set fixed address */ |
79 | IO_EMIF_MTCADDL = ATA_DEST & 0xFFFF; | 79 | IO_EMIF_MTCADDL = ATA_DEST & 0xFFFF; |
80 | IO_EMIF_DMASIZE = shortcount/2; /* 16-bits *2 = 1 word */ | 80 | IO_EMIF_DMASIZE = shortcount/2; /* 16-bits *2 = 1 word */ |
81 | IO_EMIF_DMACTL = 3; /* Select MTC->AHB and start transfer */ | 81 | IO_EMIF_DMACTL = 3; /* Select MTC->AHB and start transfer */ |
82 | 82 | ||
83 | dma_in_progress = true; | 83 | dma_in_progress = true; |
84 | wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); | 84 | wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); |
85 | 85 | ||
86 | if(shortcount % 2) | 86 | if(shortcount % 2) |
87 | { | 87 | { |
88 | unsigned short tmp; | 88 | unsigned short tmp; |
89 | tmp = ATA_DATA; | 89 | tmp = ATA_DATA; |
90 | *buf++ = tmp & 0xFF; | 90 | *buf++ = tmp & 0xFF; |
91 | *buf++ = tmp >> 8; | 91 | *buf++ = tmp >> 8; |
92 | } | 92 | } |
93 | } | 93 | } |
94 | 94 | ||
95 | void dma_ata_write(unsigned char* buf, int wordcount) | 95 | void dma_ata_write(unsigned char* buf, int wordcount) |
96 | { | 96 | { |
97 | if(dma_in_progress) | 97 | if(dma_in_progress) |
98 | wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); | 98 | wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); |
99 | 99 | ||
100 | while((unsigned long)buf & 0x1F) | 100 | while((unsigned long)buf & 0x1F) |
101 | { | 101 | { |
102 | unsigned short tmp; | 102 | unsigned short tmp; |
103 | tmp = (unsigned short) *buf++; | 103 | tmp = (unsigned short) *buf++; |
104 | tmp |= (unsigned short) *buf++ << 8; | 104 | tmp |= (unsigned short) *buf++ << 8; |
105 | SET_16BITREG(ATA_DATA, tmp); | 105 | SET_16BITREG(ATA_DATA, tmp); |
106 | wordcount--; | 106 | wordcount--; |
107 | } | 107 | } |
108 | 108 | ||
109 | if (!wordcount) | 109 | if (!wordcount) |
110 | return; | 110 | return; |
111 | 111 | ||
112 | IO_SDRAM_SDDMASEL = 0x0830; /* 32-byte burst mode transfer */ | 112 | IO_SDRAM_SDDMASEL = 0x0830; /* 32-byte burst mode transfer */ |
113 | IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */ | 113 | IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */ |
114 | IO_EMIF_AHBADDH = ((unsigned long)buf >> 16) & ~(1 << 15); /* Set variable address */ | 114 | IO_EMIF_AHBADDH = ((unsigned long)buf >> 16) & ~(1 << 15); /* Set variable address */ |
115 | IO_EMIF_AHBADDL = (unsigned long)buf & 0xFFFF; | 115 | IO_EMIF_AHBADDL = (unsigned long)buf & 0xFFFF; |
116 | IO_EMIF_MTCADDH = ( (1 << 15) | (ATA_DEST >> 16) ); /* Set fixed address */ | 116 | IO_EMIF_MTCADDH = ( (1 << 15) | (ATA_DEST >> 16) ); /* Set fixed address */ |
117 | IO_EMIF_MTCADDL = ATA_DEST & 0xFFFF; | 117 | IO_EMIF_MTCADDL = ATA_DEST & 0xFFFF; |
118 | IO_EMIF_DMASIZE = (wordcount+1)/2; | 118 | IO_EMIF_DMASIZE = (wordcount+1)/2; |
119 | IO_EMIF_DMACTL = 1; /* Select AHB->MTC and start transfer */ | 119 | IO_EMIF_DMACTL = 1; /* Select AHB->MTC and start transfer */ |
120 | 120 | ||
121 | dma_in_progress = true; | 121 | dma_in_progress = true; |
122 | wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); | 122 | wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); |
123 | } | 123 | } |
124 | 124 | ||
125 | void dma_init(void) | 125 | void dma_init(void) |
126 | { | 126 | { |
127 | IO_INTC_EINT1 |= INTR_EINT1_MTC0; /* enable MTC interrupt */ | 127 | IO_INTC_EINT1 |= INTR_EINT1_MTC0; /* enable MTC interrupt */ |
128 | wakeup_init(&transfer_completion_signal); | 128 | wakeup_init(&transfer_completion_signal); |
129 | dma_in_progress = false; | 129 | dma_in_progress = false; |
130 | } | 130 | } |