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author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-05-05 15:47:26 +0000 |
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committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-05-05 15:47:26 +0000 |
commit | e025cb1c3816cf755ed61484695dcabfdcf649b3 (patch) | |
tree | ed01d9547a314ae3d68064ebecdd94d8c4a61bb2 /firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c | |
parent | 6d12109ef7d1293810ffa3696f4dc66bcafb557b (diff) | |
download | rockbox-e025cb1c3816cf755ed61484695dcabfdcf649b3.tar.gz rockbox-e025cb1c3816cf755ed61484695dcabfdcf649b3.zip |
Split up DMA and ATA, but don't enable it (yet).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17386 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c')
-rw-r--r-- | firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c | 70 |
1 files changed, 0 insertions, 70 deletions
diff --git a/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c b/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c index 252239b62b..e43c8008c3 100644 --- a/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c +++ b/firmware/target/arm/tms320dm320/creative-zvm/ata-creativezvm.c | |||
@@ -92,79 +92,9 @@ bool ata_is_coldstart(void) | |||
92 | return true; | 92 | return true; |
93 | } | 93 | } |
94 | 94 | ||
95 | #if 0 /* Disabled as device crashes; probably due to SDRAM addresses aren't 32-bit aligned */ | ||
96 | #define CS1_START 0x50000000 | ||
97 | #define DEST_ADDR (ATA_IOBASE-CS1_START) | ||
98 | static struct wakeup transfer_completion_signal; | ||
99 | |||
100 | void MTC0(void) | ||
101 | { | ||
102 | IO_INTC_IRQ1 = 1 << IRQ_MTC0; | ||
103 | wakeup_signal(&transfer_completion_signal); | ||
104 | } | ||
105 | |||
106 | void copy_read_sectors(unsigned char* buf, int wordcount) | ||
107 | { | ||
108 | bool lasthalfword = false; | ||
109 | unsigned short tmp; | ||
110 | if(wordcount < 16) | ||
111 | { | ||
112 | _copy_read_sectors(buf, wordcount); | ||
113 | return; | ||
114 | } | ||
115 | else if((unsigned long)buf % 32) /* Not 32-byte aligned */ | ||
116 | { | ||
117 | unsigned char* bufend = buf + ((unsigned long)buf % 32); | ||
118 | if( ((unsigned long)buf % 32) % 2 ) | ||
119 | lasthalfword = true; | ||
120 | wordcount -= ((unsigned long)buf % 32) / 2; | ||
121 | do | ||
122 | { | ||
123 | tmp = ATA_DATA; | ||
124 | *buf++ = tmp >> 8; | ||
125 | *buf++ = tmp & 0xff; | ||
126 | } while (buf < bufend); /* tail loop is faster */ | ||
127 | } | ||
128 | IO_SDRAM_SDDMASEL = 0x0830; /* 32-byte burst mode transfer */ | ||
129 | IO_EMIF_AHBADDH = ((unsigned)buf >> 16) & ~(1 << 15); /* Set variable address */ | ||
130 | IO_EMIF_AHBADDL = (unsigned)buf & 0xFFFF; | ||
131 | IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */ | ||
132 | IO_EMIF_MTCADDH = ( (1 << 15) | (DEST_ADDR >> 16) ); /* Set fixed address */ | ||
133 | IO_EMIF_MTCADDL = DEST_ADDR & 0xFFFF; | ||
134 | IO_EMIF_DMASIZE = wordcount*2; | ||
135 | IO_EMIF_DMACTL = 3; /* Select MTC->AHB and start transfer */ | ||
136 | //wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); | ||
137 | while(IO_EMIF_DMACTL & 1) | ||
138 | nop; | ||
139 | if(lasthalfword) | ||
140 | { | ||
141 | *buf += wordcount * 2; | ||
142 | tmp = ATA_DATA; | ||
143 | *buf++ = tmp >> 8; | ||
144 | *buf++ = tmp & 0xff; | ||
145 | } | ||
146 | } | ||
147 | void copy_write_sectors(const unsigned char* buf, int wordcount) | ||
148 | { | ||
149 | IO_EMIF_DMAMTCSEL = 1; /* Select CS1 */ | ||
150 | IO_SDRAM_SDDMASEL = 0x0820; /* Temporarily set to standard value */ | ||
151 | IO_EMIF_AHBADDH = ((int)buf >> 16) & ~(1 << 15); /* Set variable address */ | ||
152 | IO_EMIF_AHBADDL = (int)buf & 0xFFFF; | ||
153 | IO_EMIF_MTCADDH = ( (1 << 15) | (DEST_ADDR >> 16) ); /* Set fixed address */ | ||
154 | IO_EMIF_MTCADDL = DEST_ADDR & 0xFFFF; | ||
155 | IO_EMIF_DMASIZE = wordcount; | ||
156 | IO_EMIF_DMACTL = 1; /* Select AHB->MTC and start transfer */ | ||
157 | wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK); | ||
158 | } | ||
159 | #endif | ||
160 | |||
161 | void ata_device_init(void) | 95 | void ata_device_init(void) |
162 | { | 96 | { |
163 | IO_INTC_EINT1 |= INTR_EINT1_EXT2; /* enable GIO2 interrupt */ | 97 | IO_INTC_EINT1 |= INTR_EINT1_EXT2; /* enable GIO2 interrupt */ |
164 | #if 0 | ||
165 | IO_INTC_EINT1 |= 1 << IRQ_MTC0; /* enable MTC interrupt */ | ||
166 | wakeup_init(&transfer_completion_signal); | ||
167 | #endif | ||
168 | //TODO: mimic OF inits... | 98 | //TODO: mimic OF inits... |
169 | return; | 99 | return; |
170 | } | 100 | } |