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author | Rafaël Carré <rafael.carre@gmail.com> | 2010-09-20 17:09:55 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2010-09-20 17:09:55 +0000 |
commit | 66f8fb52a9114ece70e1771119096589004d29f0 (patch) | |
tree | f1894d14dd0a26a5637acfe409c550d7a2b0443f /firmware/target/arm/tcc780x | |
parent | 72404784578162495c9986cd1563d9924ddc15be (diff) | |
download | rockbox-66f8fb52a9114ece70e1771119096589004d29f0.tar.gz rockbox-66f8fb52a9114ece70e1771119096589004d29f0.zip |
*/app.lds: remove STUBOFFSET
This is related to gdb, and gdb can only work on SH and ifp
This was mistakenly kept when app.lds was forked for each SoC
Side-effect: fix DEBUG builds when the rockbox binary is expected to
be loaded at the start of DRAM and there is no runtime relocation
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28124 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tcc780x')
-rw-r--r-- | firmware/target/arm/tcc780x/app.lds | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/firmware/target/arm/tcc780x/app.lds b/firmware/target/arm/tcc780x/app.lds index e31e46fde7..9d5570a487 100644 --- a/firmware/target/arm/tcc780x/app.lds +++ b/firmware/target/arm/tcc780x/app.lds | |||
@@ -9,16 +9,10 @@ STARTUP(target/arm/tcc780x/crt0.o) | |||
9 | #define PLUGINSIZE PLUGIN_BUFFER_SIZE | 9 | #define PLUGINSIZE PLUGIN_BUFFER_SIZE |
10 | #define CODECSIZE CODEC_SIZE | 10 | #define CODECSIZE CODEC_SIZE |
11 | 11 | ||
12 | #ifdef DEBUG | ||
13 | #define STUBOFFSET 0x10000 | ||
14 | #else | ||
15 | #define STUBOFFSET 0 | ||
16 | #endif | ||
17 | |||
18 | #include "cpu.h" | 12 | #include "cpu.h" |
19 | #define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE - TTB_SIZE | 13 | #define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE - TTB_SIZE |
20 | 14 | ||
21 | #define DRAMORIG 0x20000000 + STUBOFFSET | 15 | #define DRAMORIG 0x20000000 |
22 | #define ITCMORIG 0x00000000 | 16 | #define ITCMORIG 0x00000000 |
23 | #define ITCMSIZE 0x1000 | 17 | #define ITCMSIZE 0x1000 |
24 | #define DTCMORIG 0xA0000000 | 18 | #define DTCMORIG 0xA0000000 |