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author | Jens Arnold <amiconn@rockbox.org> | 2008-04-20 17:53:05 +0000 |
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committer | Jens Arnold <amiconn@rockbox.org> | 2008-04-20 17:53:05 +0000 |
commit | cea07eb2a4ddb72d084c7085192521613004a997 (patch) | |
tree | adbcaeac857c7fd10fa5f89f7acff0728f75f447 /firmware/target/arm/system-target.h | |
parent | 02bfba6c616a4e4aedf0e36d742598c36334e228 (diff) | |
download | rockbox-cea07eb2a4ddb72d084c7085192521613004a997.tar.gz rockbox-cea07eb2a4ddb72d084c7085192521613004a997.zip |
Fix freezing of some builds on PP5002. The PP5002 needs the not-sleep-at 0xNNNNNNN0-addresses fix everywhere when caching is enabled, not only in core_sleep(). Introduced a pair of inline functions to sleep and wake cores on PP for consistency.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17192 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-target.h')
-rw-r--r-- | firmware/target/arm/system-target.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 2a72b524f7..ebfc162cf1 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
@@ -88,6 +88,60 @@ static inline unsigned int processor_id(void) | |||
88 | return id; | 88 | return id; |
89 | } | 89 | } |
90 | 90 | ||
91 | #if CONFIG_CPU == PP5002 | ||
92 | static inline void sleep_core(int core) | ||
93 | { | ||
94 | asm volatile ( | ||
95 | /* Sleep: PP5002 crashes if the instruction that puts it to sleep is | ||
96 | * located at 0xNNNNNNN0. 4/8/C works. This sequence makes sure | ||
97 | * that the correct alternative is executed. Don't change the order | ||
98 | * of the next 4 instructions! */ | ||
99 | "tst pc, #0x0c \n" | ||
100 | "mov r0, #0xca \n" | ||
101 | "strne r0, [%[ctl]] \n" | ||
102 | "streq r0, [%[ctl]] \n" | ||
103 | "nop \n" /* nop's needed because of pipeline */ | ||
104 | "nop \n" | ||
105 | "nop \n" | ||
106 | : | ||
107 | : [ctl]"r"(&PROC_CTL(core)) | ||
108 | : "r0" | ||
109 | ); | ||
110 | } | ||
111 | static inline void wake_core(int core) | ||
112 | { | ||
113 | asm volatile ( | ||
114 | "mov r0, #0xce \n" | ||
115 | "str r0, [%[ctl]] \n" | ||
116 | : | ||
117 | : [ctl]"r"(&PROC_CTL(core)) | ||
118 | : "r0" | ||
119 | ); | ||
120 | } | ||
121 | #else /* PP502x */ | ||
122 | static inline void sleep_core(int core) | ||
123 | { | ||
124 | asm volatile ( | ||
125 | "mov r0, #0x80000000 \n" | ||
126 | "str r0, [%[ctl]] \n" | ||
127 | "nop \n" | ||
128 | : | ||
129 | : [ctl]"r"(&PROC_CTL(core)) | ||
130 | : "r0" | ||
131 | ); | ||
132 | } | ||
133 | static inline void wake_core(int core) | ||
134 | { | ||
135 | asm volatile ( | ||
136 | "mov r0, #0 \n" | ||
137 | "str r0, [%[ctl]] \n" | ||
138 | : | ||
139 | : [ctl]"r"(&PROC_CTL(core)) | ||
140 | : "r0" | ||
141 | ); | ||
142 | } | ||
143 | #endif | ||
144 | |||
91 | #ifdef BOOTLOADER | 145 | #ifdef BOOTLOADER |
92 | /* All addresses within rockbox are in IRAM in the bootloader so | 146 | /* All addresses within rockbox are in IRAM in the bootloader so |
93 | are therefore uncached */ | 147 | are therefore uncached */ |