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author | Michael Sevakis <jethead71@rockbox.org> | 2007-04-14 01:18:06 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2007-04-14 01:18:06 +0000 |
commit | 20c6bf50fe89c94e57ba7920d667ad28541c3ce1 (patch) | |
tree | 9588e3ba1703323744dd5681941f4feb8a5778ee /firmware/target/arm/system-target.h | |
parent | ca6f4abcf17a84d52646a8a6b305ab1011efe6d0 (diff) | |
download | rockbox-20c6bf50fe89c94e57ba7920d667ad28541c3ce1.tar.gz rockbox-20c6bf50fe89c94e57ba7920d667ad28541c3ce1.zip |
Do the target shuffle again a better way by including from higher levels
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13151 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-target.h')
-rw-r--r-- | firmware/target/arm/system-target.h | 142 |
1 files changed, 23 insertions, 119 deletions
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index ceb8be2079..2b72e9293e 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
@@ -8,6 +8,7 @@ | |||
8 | * $Id$ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2002 by Alan Korr | 10 | * Copyright (C) 2002 by Alan Korr |
11 | * Copyright (C) 2007 by Michael Sevakis | ||
11 | * | 12 | * |
12 | * All files in this archive are subject to the GNU General Public License. | 13 | * All files in this archive are subject to the GNU General Public License. |
13 | * See the file COPYING in the source tree root for full license agreement. | 14 | * See the file COPYING in the source tree root for full license agreement. |
@@ -19,137 +20,40 @@ | |||
19 | #ifndef SYSTEM_TARGET_H | 20 | #ifndef SYSTEM_TARGET_H |
20 | #define SYSTEM_TARGET_H | 21 | #define SYSTEM_TARGET_H |
21 | 22 | ||
22 | #define nop \ | 23 | #include "system-arm.h" |
23 | asm volatile ("nop") | ||
24 | 24 | ||
25 | /* This gets too complicated otherwise with all the ARM variation and would | 25 | #define inl(a) (*(volatile unsigned long *) (a)) |
26 | have conflicts with another system-target.h elsewhere so include a | 26 | #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) |
27 | subheader from here. */ | 27 | #define inb(a) (*(volatile unsigned char *) (a)) |
28 | #define outb(a,b) (*(volatile unsigned char *) (b) = (a)) | ||
29 | #define inw(a) (*(volatile unsigned short *) (a)) | ||
30 | #define outw(a,b) (*(volatile unsigned short *) (b) = (a)) | ||
31 | extern unsigned int ipod_hw_rev; | ||
28 | 32 | ||
29 | #ifdef CPU_PP | 33 | static inline void udelay(unsigned usecs) |
30 | #include "system-pp.h" | ||
31 | #elif CONFIG_CPU == S3C2440 | ||
32 | #include "system-meg-fx.h" | ||
33 | #endif | ||
34 | |||
35 | /* TODO: Implement set_irq_level and check CPU frequencies */ | ||
36 | |||
37 | #if CONFIG_CPU == S3C2440 | ||
38 | |||
39 | #define CPUFREQ_DEFAULT 98784000 | ||
40 | #define CPUFREQ_NORMAL 98784000 | ||
41 | #define CPUFREQ_MAX 296352000 | ||
42 | |||
43 | #elif CONFIG_CPU == PNX0101 | ||
44 | |||
45 | #define CPUFREQ_DEFAULT 12000000 | ||
46 | #define CPUFREQ_NORMAL 48000000 | ||
47 | #define CPUFREQ_MAX 60000000 | ||
48 | |||
49 | #else | ||
50 | |||
51 | #define CPUFREQ_DEFAULT_MULT 8 | ||
52 | #define CPUFREQ_DEFAULT 24000000 | ||
53 | #define CPUFREQ_NORMAL_MULT 10 | ||
54 | #define CPUFREQ_NORMAL 30000000 | ||
55 | #define CPUFREQ_MAX_MULT 25 | ||
56 | #define CPUFREQ_MAX 75000000 | ||
57 | |||
58 | #endif | ||
59 | |||
60 | static inline uint16_t swap16(uint16_t value) | ||
61 | /* | ||
62 | result[15..8] = value[ 7..0]; | ||
63 | result[ 7..0] = value[15..8]; | ||
64 | */ | ||
65 | { | 34 | { |
66 | return (value >> 8) | (value << 8); | 35 | unsigned stop = USEC_TIMER + usecs; |
36 | while (TIME_BEFORE(USEC_TIMER, stop)); | ||
67 | } | 37 | } |
68 | 38 | ||
69 | static inline uint32_t swap32(uint32_t value) | 39 | unsigned int current_core(void); |
70 | /* | ||
71 | result[31..24] = value[ 7.. 0]; | ||
72 | result[23..16] = value[15.. 8]; | ||
73 | result[15.. 8] = value[23..16]; | ||
74 | result[ 7.. 0] = value[31..24]; | ||
75 | */ | ||
76 | { | ||
77 | uint32_t tmp; | ||
78 | 40 | ||
79 | asm volatile ( | 41 | #if CONFIG_CPU != PP5002 |
80 | "eor %1, %0, %0, ror #16 \n\t" | ||
81 | "bic %1, %1, #0xff0000 \n\t" | ||
82 | "mov %0, %0, ror #8 \n\t" | ||
83 | "eor %0, %0, %1, lsr #8 \n\t" | ||
84 | : "+r" (value), "=r" (tmp) | ||
85 | ); | ||
86 | return value; | ||
87 | } | ||
88 | 42 | ||
89 | static inline uint32_t swap_odd_even32(uint32_t value) | 43 | #define HAVE_INVALIDATE_ICACHE |
44 | static inline void invalidate_icache(void) | ||
90 | { | 45 | { |
91 | /* | 46 | outl(inl(0xf000f044) | 0x6, 0xf000f044); |
92 | result[31..24],[15.. 8] = value[23..16],[ 7.. 0] | 47 | while ((CACHE_CTL & 0x8000) != 0); |
93 | result[23..16],[ 7.. 0] = value[31..24],[15.. 8] | ||
94 | */ | ||
95 | uint32_t tmp; | ||
96 | |||
97 | asm volatile ( /* ABCD */ | ||
98 | "bic %1, %0, #0x00ff00 \n\t" /* AB.D */ | ||
99 | "bic %0, %0, #0xff0000 \n\t" /* A.CD */ | ||
100 | "mov %0, %0, lsr #8 \n\t" /* .A.C */ | ||
101 | "orr %0, %0, %1, lsl #8 \n\t" /* B.D.|.A.C */ | ||
102 | : "+r" (value), "=r" (tmp) /* BADC */ | ||
103 | ); | ||
104 | return value; | ||
105 | } | 48 | } |
106 | 49 | ||
107 | #define HIGHEST_IRQ_LEVEL (1) | 50 | #define HAVE_FLUSH_ICACHE |
108 | 51 | static inline void flush_icache(void) | |
109 | static inline int set_irq_level(int level) | ||
110 | { | ||
111 | unsigned long cpsr; | ||
112 | /* Read the old level and set the new one */ | ||
113 | asm volatile ("mrs %0,cpsr" : "=r" (cpsr)); | ||
114 | asm volatile ("msr cpsr_c,%0" | ||
115 | : : "r" ((cpsr & ~0x80) | (level << 7))); | ||
116 | return (cpsr >> 7) & 1; | ||
117 | } | ||
118 | |||
119 | static inline void set_fiq_handler(void(*fiq_handler)(void)) | ||
120 | { | 52 | { |
121 | /* Install the FIQ handler */ | 53 | outl(inl(0xf000f044) | 0x2, 0xf000f044); |
122 | *((unsigned int*)(15*4)) = (unsigned int)fiq_handler; | 54 | while ((CACHE_CTL & 0x8000) != 0); |
123 | } | 55 | } |
124 | 56 | ||
125 | static inline void enable_fiq(void) | 57 | #endif /* CONFIG_CPU */ |
126 | { | ||
127 | /* Clear FIQ disable bit */ | ||
128 | asm volatile ( | ||
129 | "mrs r0, cpsr \n"\ | ||
130 | "bic r0, r0, #0x40 \n"\ | ||
131 | "msr cpsr_c, r0 " | ||
132 | : : : "r0" | ||
133 | ); | ||
134 | } | ||
135 | |||
136 | static inline void disable_fiq(void) | ||
137 | { | ||
138 | /* Set FIQ disable bit */ | ||
139 | asm volatile ( | ||
140 | "mrs r0, cpsr \n"\ | ||
141 | "orr r0, r0, #0x40 \n"\ | ||
142 | "msr cpsr_c, r0 " | ||
143 | : : : "r0" | ||
144 | ); | ||
145 | } | ||
146 | |||
147 | #if CONFIG_CPU == PNX0101 | ||
148 | typedef void (*interrupt_handler_t)(void); | ||
149 | |||
150 | void irq_set_int_handler(int n, interrupt_handler_t handler); | ||
151 | void irq_enable_int(int n); | ||
152 | void irq_disable_int(int n); | ||
153 | #endif | ||
154 | 58 | ||
155 | #endif /* SYSTEM_TARGET_H */ | 59 | #endif /* SYSTEM_TARGET_H */ |