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author | Jens Arnold <amiconn@rockbox.org> | 2007-07-02 05:16:40 +0000 |
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committer | Jens Arnold <amiconn@rockbox.org> | 2007-07-02 05:16:40 +0000 |
commit | fe23dc8f15e9d01ea634d10b334984f1d8760007 (patch) | |
tree | 5e12734e3f510c393ca272048f5425435ea26bf3 /firmware/target/arm/system-pp502x.c | |
parent | 36de1a4d084da18af22d47a435a4eebcf3c50fb2 (diff) | |
download | rockbox-fe23dc8f15e9d01ea634d10b334984f1d8760007.tar.gz rockbox-fe23dc8f15e9d01ea634d10b334984f1d8760007.zip |
Improved CPU clock setup for PP502x. PP5020 and PP5022 are not register compatible here, so define the PP5022 targets properly, and introduce a CPU_PP502x macro for easier family check. Improves stability on PP5020 (less freezing, tested with Mini G1) and reduces clock change penalty (500us on PP5020; uses the relock bit on PP5022).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13763 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-pp502x.c')
-rw-r--r-- | firmware/target/arm/system-pp502x.c | 41 |
1 files changed, 15 insertions, 26 deletions
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c index 49ffdd300b..658ea0eeb3 100644 --- a/firmware/target/arm/system-pp502x.c +++ b/firmware/target/arm/system-pp502x.c | |||
@@ -151,7 +151,7 @@ static void ipod_init_cache(void) | |||
151 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 151 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |
152 | void set_cpu_frequency(long frequency) | 152 | void set_cpu_frequency(long frequency) |
153 | { | 153 | { |
154 | unsigned long postmult; | 154 | unsigned long postmult, pll_control; |
155 | 155 | ||
156 | # if NUM_CORES > 1 | 156 | # if NUM_CORES > 1 |
157 | /* Using mutex or spinlock isn't safe here. */ | 157 | /* Using mutex or spinlock isn't safe here. */ |
@@ -168,35 +168,24 @@ void set_cpu_frequency(long frequency) | |||
168 | 168 | ||
169 | /* Enable PLL? */ | 169 | /* Enable PLL? */ |
170 | outl(inl(0x70000020) | (1<<30), 0x70000020); | 170 | outl(inl(0x70000020) | (1<<30), 0x70000020); |
171 | 171 | ||
172 | /* Select 24MHz crystal as clock source? */ | 172 | /* Select 24MHz crystal as clock source? */ |
173 | outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020); | 173 | outl((inl(0x60006020) & 0x0ffffff0) | 0x10000002, 0x60006020); |
174 | 174 | ||
175 | /* Clock frequency = (24/8)*postmult */ | 175 | /* Clock frequency = (24/8)*postmult */ |
176 | outl(0xaa020000 | 8 | (postmult << 8), 0x60006034); | 176 | pll_control = 0x8a020000 | 8 | (postmult << 8); |
177 | 177 | outl(pll_control, 0x60006034); | |
178 | /* Wait for PLL relock? */ | 178 | # if CONFIG_CPU == PP5020 |
179 | udelay(2000); | 179 | outl(0xd198, 0x6000603c); /* magic sequence */ |
180 | outl(pll_control, 0x60006034); | ||
181 | udelay(500); /* wait for relock */ | ||
182 | # else /* PP5022, PP5024 */ | ||
183 | while (!(inl(0x6000603c) & 0x80000000)); /* wait for relock */ | ||
184 | # endif | ||
180 | 185 | ||
181 | /* Select PLL as clock source? */ | 186 | /* Select PLL as clock source? */ |
182 | outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020); | 187 | outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020); |
183 | 188 | ||
184 | # if defined(IPOD_COLOR) || defined(IPOD_4G) || defined(IPOD_MINI) || defined(IRIVER_H10) || defined(IRIVER_H10_5GB) | ||
185 | /* We don't know why the timer interrupt gets disabled on the PP5020 | ||
186 | based ipods, but without the following line, the 4Gs will freeze | ||
187 | when CPU frequency changing is enabled. | ||
188 | |||
189 | Note also that a simple "CPU_INT_EN = TIMER1_MASK;" (as used | ||
190 | elsewhere to enable interrupts) doesn't work, we need "|=". | ||
191 | |||
192 | It's not needed on the PP5021 and PP5022 ipods. | ||
193 | */ | ||
194 | |||
195 | /* unmask interrupt source */ | ||
196 | CPU_INT_EN |= TIMER1_MASK; | ||
197 | COP_INT_EN |= TIMER1_MASK; | ||
198 | # endif | ||
199 | |||
200 | # if NUM_CORES > 1 | 189 | # if NUM_CORES > 1 |
201 | boostctrl_mtx.locked = 0; | 190 | boostctrl_mtx.locked = 0; |
202 | # endif | 191 | # endif |
@@ -213,9 +202,9 @@ void ipod_set_cpu_frequency(void) | |||
213 | outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020); | 202 | outl((inl(0x60006020) & 0x0fffff0f) | 0x20000020, 0x60006020); |
214 | 203 | ||
215 | /* Clock frequency = (24/8)*25 = 75MHz */ | 204 | /* Clock frequency = (24/8)*25 = 75MHz */ |
216 | outl(0xaa020000 | 8 | (25 << 8), 0x60006034); | 205 | outl(0x8a020000 | 8 | (25 << 8), 0x60006034); |
217 | /* Wait for PLL relock? */ | 206 | /* Wait for PLL relock? */ |
218 | udelay(2000); | 207 | udelay(500); |
219 | 208 | ||
220 | /* Select PLL as clock source? */ | 209 | /* Select PLL as clock source? */ |
221 | outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020); | 210 | outl((inl(0x60006020) & 0x0fffff0f) | 0x20000070, 0x60006020); |