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author | Michael Sevakis <jethead71@rockbox.org> | 2017-01-21 14:18:37 -0500 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2017-01-21 14:25:52 -0500 |
commit | 3e738661108fb2a8e3474c6336c2a5c2668f82b6 (patch) | |
tree | c3c7bc51c4329ab6652fd2550a241a56bbafda1f /firmware/target/arm/system-arm.h | |
parent | da464572318a34f4791ccb419acbf0a470b810e6 (diff) | |
download | rockbox-3e738661108fb2a8e3474c6336c2a5c2668f82b6.tar.gz rockbox-3e738661108fb2a8e3474c6336c2a5c2668f82b6.zip |
Add CPU mode asserts to kernel on blocking functions.
This scourge finds it's way back in far too often.
Right now, only defined for ARM.
Have fun!
Change-Id: Ib21be09ebf71dec10dc652a7a664779251f49644
Diffstat (limited to 'firmware/target/arm/system-arm.h')
-rw-r--r-- | firmware/target/arm/system-arm.h | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/firmware/target/arm/system-arm.h b/firmware/target/arm/system-arm.h index 719ec82f1b..2d8c6f2c9f 100644 --- a/firmware/target/arm/system-arm.h +++ b/firmware/target/arm/system-arm.h | |||
@@ -76,9 +76,32 @@ void __div0(void); | |||
76 | #define ints_enabled_checkval(val) \ | 76 | #define ints_enabled_checkval(val) \ |
77 | (((val) & IRQ_FIQ_STATUS) == 0) | 77 | (((val) & IRQ_FIQ_STATUS) == 0) |
78 | 78 | ||
79 | #define CPU_MODE_USER 0x10 | ||
80 | #define CPU_MODE_FIQ 0x11 | ||
81 | #define CPU_MODE_IRQ 0x12 | ||
82 | #define CPU_MODE_SVC 0x13 | ||
83 | #define CPU_MODE_ABT 0x17 | ||
84 | #define CPU_MODE_UNDEF 0x1b | ||
85 | #define CPU_MODE_SYS 0x1f | ||
86 | |||
79 | /* We run in SYS mode */ | 87 | /* We run in SYS mode */ |
88 | #define CPU_MODE_THREAD_CONTEXT CPU_MODE_SYS | ||
89 | |||
80 | #define is_thread_context() \ | 90 | #define is_thread_context() \ |
81 | (get_processor_mode() == 0x1f) | 91 | (get_processor_mode() == CPU_MODE_THREAD_CONTEXT) |
92 | |||
93 | /* Assert that the processor is in the desired execution mode | ||
94 | * mode: Processor mode value to test for | ||
95 | * rstatus...: Provide if you already have the value saved, otherwise leave | ||
96 | * blank to get it automatically. | ||
97 | */ | ||
98 | #define ASSERT_CPU_MODE(mode, rstatus...) \ | ||
99 | ({ unsigned long __massert = (mode); \ | ||
100 | unsigned long __mproc = *#rstatus ? \ | ||
101 | ((rstatus +0) & 0x1f) : get_processor_mode(); \ | ||
102 | if (__mproc != __massert) \ | ||
103 | panicf("Incorrect CPU mode in %s (0x%02lx!=0x%02lx)", \ | ||
104 | __func__, __mproc, __massert); }) | ||
82 | 105 | ||
83 | /* Core-level interrupt masking */ | 106 | /* Core-level interrupt masking */ |
84 | 107 | ||