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author | Michael Sevakis <jethead71@rockbox.org> | 2012-01-08 22:29:25 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2012-01-08 22:29:25 +0000 |
commit | 307cb049485cc20140b85aa78f8e2677e8df5851 (patch) | |
tree | eaadfd7266e4e97e69bccd68655140dd9f1ef061 /firmware/target/arm/system-arm.h | |
parent | 5e21bbf5757163725f4bd2909fc7aaa548f61fc3 (diff) | |
download | rockbox-307cb049485cc20140b85aa78f8e2677e8df5851.tar.gz rockbox-307cb049485cc20140b85aa78f8e2677e8df5851.zip |
AS3525v1/2: Enable nested handling of interrupts
Mostly for the sake of reducing latency for audio servicing where other service
routines can take a long time to complete, leading to occasional drops of a
few samples, especially in recording, where they are fairly frequent.
One mystery that remains is GPIOA IRQ being interrupted causes strange
undefined instruction exceptions, most easily produced on my Fuze V2 with a
scrollwheel. Making GPIOA the top ISR for now, thus not interruptible, cures it.
SVC mode is used during the actual calls. Hopefully the SVC stack size is
sufficient. Prologue and epilogue code only uses the IRQ stack and is large
enough.
Any routine code that should not be interrupted should disable IRQ itself from
here on in.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31642 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-arm.h')
-rw-r--r-- | firmware/target/arm/system-arm.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/firmware/target/arm/system-arm.h b/firmware/target/arm/system-arm.h index b3630a8473..ffce77a176 100644 --- a/firmware/target/arm/system-arm.h +++ b/firmware/target/arm/system-arm.h | |||
@@ -76,6 +76,9 @@ void __div0(void); | |||
76 | #define ints_enabled_checkval(val) \ | 76 | #define ints_enabled_checkval(val) \ |
77 | (((val) & IRQ_FIQ_STATUS) == 0) | 77 | (((val) & IRQ_FIQ_STATUS) == 0) |
78 | 78 | ||
79 | /* We run in SYS mode */ | ||
80 | #define is_thread_context() \ | ||
81 | (get_processor_mode() == 0x1f) | ||
79 | 82 | ||
80 | /* Core-level interrupt masking */ | 83 | /* Core-level interrupt masking */ |
81 | 84 | ||
@@ -109,6 +112,13 @@ static inline bool interrupt_enabled(int status) | |||
109 | return (cpsr & status) == 0; | 112 | return (cpsr & status) == 0; |
110 | } | 113 | } |
111 | 114 | ||
115 | static inline unsigned long get_processor_mode(void) | ||
116 | { | ||
117 | unsigned long cpsr; | ||
118 | asm ("mrs %0, cpsr" : "=r"(cpsr)); | ||
119 | return cpsr & 0x1f; | ||
120 | } | ||
121 | |||
112 | /* ARM_ARCH version section for architecture*/ | 122 | /* ARM_ARCH version section for architecture*/ |
113 | 123 | ||
114 | #if ARM_ARCH >= 6 | 124 | #if ARM_ARCH >= 6 |