diff options
author | Michael Sevakis <jethead71@rockbox.org> | 2007-04-14 01:18:06 +0000 |
---|---|---|
committer | Michael Sevakis <jethead71@rockbox.org> | 2007-04-14 01:18:06 +0000 |
commit | 20c6bf50fe89c94e57ba7920d667ad28541c3ce1 (patch) | |
tree | 9588e3ba1703323744dd5681941f4feb8a5778ee /firmware/target/arm/system-arm.h | |
parent | ca6f4abcf17a84d52646a8a6b305ab1011efe6d0 (diff) | |
download | rockbox-20c6bf50fe89c94e57ba7920d667ad28541c3ce1.tar.gz rockbox-20c6bf50fe89c94e57ba7920d667ad28541c3ce1.zip |
Do the target shuffle again a better way by including from higher levels
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13151 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-arm.h')
-rw-r--r-- | firmware/target/arm/system-arm.h | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/firmware/target/arm/system-arm.h b/firmware/target/arm/system-arm.h new file mode 100644 index 0000000000..7126350a64 --- /dev/null +++ b/firmware/target/arm/system-arm.h | |||
@@ -0,0 +1,130 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Alan Korr | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #ifndef SYSTEM_ARM_H | ||
20 | #define SYSTEM_ARM_H | ||
21 | |||
22 | #define nop \ | ||
23 | asm volatile ("nop") | ||
24 | |||
25 | /* This gets too complicated otherwise with all the ARM variation and would | ||
26 | have conflicts with another system-target.h elsewhere so include a | ||
27 | subheader from here. */ | ||
28 | |||
29 | /* TODO: Implement set_irq_level and check CPU frequencies */ | ||
30 | |||
31 | #if CONFIG_CPU != S3C2440 && CONFIG_CPU != PNX0101 | ||
32 | |||
33 | /* TODO: Finish targeting this stuff */ | ||
34 | #define CPUFREQ_DEFAULT_MULT 8 | ||
35 | #define CPUFREQ_DEFAULT 24000000 | ||
36 | #define CPUFREQ_NORMAL_MULT 10 | ||
37 | #define CPUFREQ_NORMAL 30000000 | ||
38 | #define CPUFREQ_MAX_MULT 25 | ||
39 | #define CPUFREQ_MAX 75000000 | ||
40 | |||
41 | #endif | ||
42 | |||
43 | static inline uint16_t swap16(uint16_t value) | ||
44 | /* | ||
45 | result[15..8] = value[ 7..0]; | ||
46 | result[ 7..0] = value[15..8]; | ||
47 | */ | ||
48 | { | ||
49 | return (value >> 8) | (value << 8); | ||
50 | } | ||
51 | |||
52 | static inline uint32_t swap32(uint32_t value) | ||
53 | /* | ||
54 | result[31..24] = value[ 7.. 0]; | ||
55 | result[23..16] = value[15.. 8]; | ||
56 | result[15.. 8] = value[23..16]; | ||
57 | result[ 7.. 0] = value[31..24]; | ||
58 | */ | ||
59 | { | ||
60 | uint32_t tmp; | ||
61 | |||
62 | asm volatile ( | ||
63 | "eor %1, %0, %0, ror #16 \n\t" | ||
64 | "bic %1, %1, #0xff0000 \n\t" | ||
65 | "mov %0, %0, ror #8 \n\t" | ||
66 | "eor %0, %0, %1, lsr #8 \n\t" | ||
67 | : "+r" (value), "=r" (tmp) | ||
68 | ); | ||
69 | return value; | ||
70 | } | ||
71 | |||
72 | static inline uint32_t swap_odd_even32(uint32_t value) | ||
73 | { | ||
74 | /* | ||
75 | result[31..24],[15.. 8] = value[23..16],[ 7.. 0] | ||
76 | result[23..16],[ 7.. 0] = value[31..24],[15.. 8] | ||
77 | */ | ||
78 | uint32_t tmp; | ||
79 | |||
80 | asm volatile ( /* ABCD */ | ||
81 | "bic %1, %0, #0x00ff00 \n\t" /* AB.D */ | ||
82 | "bic %0, %0, #0xff0000 \n\t" /* A.CD */ | ||
83 | "mov %0, %0, lsr #8 \n\t" /* .A.C */ | ||
84 | "orr %0, %0, %1, lsl #8 \n\t" /* B.D.|.A.C */ | ||
85 | : "+r" (value), "=r" (tmp) /* BADC */ | ||
86 | ); | ||
87 | return value; | ||
88 | } | ||
89 | |||
90 | #define HIGHEST_IRQ_LEVEL (1) | ||
91 | |||
92 | static inline int set_irq_level(int level) | ||
93 | { | ||
94 | unsigned long cpsr; | ||
95 | /* Read the old level and set the new one */ | ||
96 | asm volatile ("mrs %0,cpsr" : "=r" (cpsr)); | ||
97 | asm volatile ("msr cpsr_c,%0" | ||
98 | : : "r" ((cpsr & ~0x80) | (level << 7))); | ||
99 | return (cpsr >> 7) & 1; | ||
100 | } | ||
101 | |||
102 | static inline void set_fiq_handler(void(*fiq_handler)(void)) | ||
103 | { | ||
104 | /* Install the FIQ handler */ | ||
105 | *((unsigned int*)(15*4)) = (unsigned int)fiq_handler; | ||
106 | } | ||
107 | |||
108 | static inline void enable_fiq(void) | ||
109 | { | ||
110 | /* Clear FIQ disable bit */ | ||
111 | asm volatile ( | ||
112 | "mrs r0, cpsr \n"\ | ||
113 | "bic r0, r0, #0x40 \n"\ | ||
114 | "msr cpsr_c, r0 " | ||
115 | : : : "r0" | ||
116 | ); | ||
117 | } | ||
118 | |||
119 | static inline void disable_fiq(void) | ||
120 | { | ||
121 | /* Set FIQ disable bit */ | ||
122 | asm volatile ( | ||
123 | "mrs r0, cpsr \n"\ | ||
124 | "orr r0, r0, #0x40 \n"\ | ||
125 | "msr cpsr_c, r0 " | ||
126 | : : : "r0" | ||
127 | ); | ||
128 | } | ||
129 | |||
130 | #endif /* SYSTEM_ARM_H */ | ||