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author | Cástor Muñoz <cmvidal@gmail.com> | 2014-12-01 02:33:41 +0100 |
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committer | Cástor Muñoz <cmvidal@gmail.com> | 2014-12-08 03:07:44 +0100 |
commit | bfb63f801707e281317789c1a63ce745d5bae6e2 (patch) | |
tree | 2f4d4d47b0216cd143ccc9d90a84204695f787e3 /firmware/target/arm/s5l8702/timer-s5l8702.c | |
parent | 8618f2c227e7daed2d1dd566090c2c4588533470 (diff) | |
download | rockbox-bfb63f801707e281317789c1a63ce745d5bae6e2.tar.gz rockbox-bfb63f801707e281317789c1a63ce745d5bae6e2.zip |
iPod Classic: minor modifications in TIMER
The current behaviour should not change.
Change-Id: Ia8f44cdccf41dbc3881722f9aebab91de51a9bc5
Diffstat (limited to 'firmware/target/arm/s5l8702/timer-s5l8702.c')
-rw-r--r-- | firmware/target/arm/s5l8702/timer-s5l8702.c | 33 |
1 files changed, 18 insertions, 15 deletions
diff --git a/firmware/target/arm/s5l8702/timer-s5l8702.c b/firmware/target/arm/s5l8702/timer-s5l8702.c index 7c69ab123a..5b145ed7e3 100644 --- a/firmware/target/arm/s5l8702/timer-s5l8702.c +++ b/firmware/target/arm/s5l8702/timer-s5l8702.c | |||
@@ -38,8 +38,10 @@ void INT_TIMERF(void) | |||
38 | 38 | ||
39 | bool timer_set(long cycles, bool start) | 39 | bool timer_set(long cycles, bool start) |
40 | { | 40 | { |
41 | int tf_en = TFCMD & (1 << 0); /* save TF_EN status */ | ||
42 | |||
41 | /* stop timer */ | 43 | /* stop timer */ |
42 | TFCMD = (0 << 0); /* TF_ENABLE */ | 44 | TFCMD = (0 << 0); /* TF_EN = disable */ |
43 | 45 | ||
44 | /* optionally unregister any previously registered timer user */ | 46 | /* optionally unregister any previously registered timer user */ |
45 | if (start) { | 47 | if (start) { |
@@ -49,33 +51,34 @@ bool timer_set(long cycles, bool start) | |||
49 | } | 51 | } |
50 | } | 52 | } |
51 | 53 | ||
52 | /* There is an odd behaviour when the 32-bit timers are launched | ||
53 | for the first time, the interrupt status bits are set and an | ||
54 | unexpected interrupt is generated if they are enabled. A way to | ||
55 | workaround this is to write the data registers before clearing | ||
56 | the counter. */ | ||
57 | TFDATA0 = cycles; | ||
58 | TFCMD = (1 << 1); /* TF_CLR */ | ||
59 | |||
60 | /* configure timer */ | 54 | /* configure timer */ |
61 | TFCON = (1 << 12) | /* TF_INT0_EN */ | 55 | TFCON = (1 << 12) | /* TF_INT0_EN */ |
62 | (4 << 8) | /* TF_CS, 4 = ECLK / 1 */ | 56 | (4 << 8) | /* TF_CS = ECLK / 1 */ |
63 | (1 << 6) | /* use ECLK (12MHz) */ | 57 | (1 << 6) | /* select ECLK (12 MHz) */ |
64 | (0 << 4); /* TF_MODE_SEL, 0 = interval mode */ | 58 | (0 << 4); /* TF_MODE_SEL = interval mode */ |
65 | TFPRE = 0; /* no prescaler */ | 59 | TFPRE = 0; /* no prescaler */ |
60 | TFDATA0 = cycles; /* set interval period */ | ||
66 | 61 | ||
67 | TFCMD = (1 << 0); /* TF_ENABLE */ | 62 | /* After the configuration, we must write '1' in TF_CLR to |
63 | * initialize the timer (s5l8700 DS): | ||
64 | * - Clear the counter register. | ||
65 | * - The value of TF_START is set to TF_OUT. | ||
66 | * - TF_DATA0 and TF_DATA1 are updated to the internal buffers. | ||
67 | * - Initialize the state of the previously captured signal. | ||
68 | */ | ||
69 | TFCMD = (1 << 1) | /* TF_CLR = initialize timer */ | ||
70 | (tf_en << 0); /* TF_EN = restore previous status */ | ||
68 | 71 | ||
69 | return true; | 72 | return true; |
70 | } | 73 | } |
71 | 74 | ||
72 | bool timer_start(void) | 75 | bool timer_start(void) |
73 | { | 76 | { |
74 | TFCMD = (1 << 0); /* TF_ENABLE */ | 77 | TFCMD = (1 << 0); /* TF_EN = enable */ |
75 | return true; | 78 | return true; |
76 | } | 79 | } |
77 | 80 | ||
78 | void timer_stop(void) | 81 | void timer_stop(void) |
79 | { | 82 | { |
80 | TFCMD = (0 << 0); /* TF_ENABLE */ | 83 | TFCMD = (0 << 0); /* TF_EN = disable */ |
81 | } | 84 | } |