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authorCástor Muñoz <cmvidal@gmail.com>2014-12-01 02:33:41 +0100
committerCástor Muñoz <cmvidal@gmail.com>2014-12-08 03:07:44 +0100
commitbfb63f801707e281317789c1a63ce745d5bae6e2 (patch)
tree2f4d4d47b0216cd143ccc9d90a84204695f787e3 /firmware/target/arm/s5l8702/kernel-s5l8702.c
parent8618f2c227e7daed2d1dd566090c2c4588533470 (diff)
downloadrockbox-bfb63f801707e281317789c1a63ce745d5bae6e2.tar.gz
rockbox-bfb63f801707e281317789c1a63ce745d5bae6e2.zip
iPod Classic: minor modifications in TIMER
The current behaviour should not change. Change-Id: Ia8f44cdccf41dbc3881722f9aebab91de51a9bc5
Diffstat (limited to 'firmware/target/arm/s5l8702/kernel-s5l8702.c')
-rw-r--r--firmware/target/arm/s5l8702/kernel-s5l8702.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/firmware/target/arm/s5l8702/kernel-s5l8702.c b/firmware/target/arm/s5l8702/kernel-s5l8702.c
index b39b384696..6a70981c93 100644
--- a/firmware/target/arm/s5l8702/kernel-s5l8702.c
+++ b/firmware/target/arm/s5l8702/kernel-s5l8702.c
@@ -39,19 +39,16 @@ void tick_start(unsigned int interval_in_ms)
39{ 39{
40 int cycles = 10 * interval_in_ms; 40 int cycles = 10 * interval_in_ms;
41 41
42 /* configure timer for 10 kHz (external source) */ 42 /* configure timer for 10 kHz (12 MHz / 16 / 75) */
43 TBCMD = (1 << 1); /* TB_CLR */ 43 TBCMD = (1 << 1); /* TB_CLR */
44 TBPRE = 75 - 1; /* prescaler */ /* 12 MHz / 16 / 75 = 10 KHz */ 44 TBPRE = 75 - 1; /* prescaler */
45 TBCON = (0 << 13) | /* TB_INT1_EN */ 45 TBCON = (0 << 13) | /* TB_INT1_EN */
46 (1 << 12) | /* TB_INT0_EN */ 46 (1 << 12) | /* TB_INT0_EN */
47 (0 << 11) | /* TB_START */ 47 (0 << 11) | /* TB_START */
48 (2 << 8) | /* TB_CS = PCLK / 16 */ 48 (2 << 8) | /* TB_CS = ECLK / 16 */
49 (1 << 6) | /* UNKNOWN bit */ /* external 12 MHz clock (?) */ 49 (1 << 6) | /* select ECLK (12 MHz) */
50 (0 << 4); /* TB_MODE_SEL = interval mode */ 50 (0 << 4); /* TB_MODE_SEL = interval mode */
51 TBDATA0 = cycles; /* set interval period */ 51 TBDATA0 = cycles; /* set interval period */
52 TBCMD = (1 << 0); /* TB_EN */ 52 TBCMD = (1 << 0); /* TB_EN */
53
54 /* enable timer interrupt */
55 VIC0INTENABLE = 1 << IRQ_TIMER;
56} 53}
57 54