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author | Cástor Muñoz <cmvidal@gmail.com> | 2016-05-12 02:14:48 +0200 |
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committer | Cástor Muñoz <cmvidal@gmail.com> | 2016-05-13 23:23:01 +0200 |
commit | 5017523a6b1ea9d230d8b8cf801ad3adbe7f43f5 (patch) | |
tree | db521d53b171dde30f8b083177bb3c322cd43cf6 /firmware/target/arm/s5l8700/uart-s5l8701.c | |
parent | 8fb67f48ab57770c3233352de17846a8a773192a (diff) | |
download | rockbox-5017523a6b1ea9d230d8b8cf801ad3adbe7f43f5.tar.gz rockbox-5017523a6b1ea9d230d8b8cf801ad3adbe7f43f5.zip |
Add UART suuport for s5l8700 and s5l8701
Add UART support for s5l8700/1 using the UC870X UART controller,
actually the functionallity is disabled and must be enabled for
each individual target. Tested on iPod Nano 2G (s5l8701), not
tested on s5l8700.
Change-Id: Ic0f216bb871502d355a70e4b658e536a2c0976a9
Diffstat (limited to 'firmware/target/arm/s5l8700/uart-s5l8701.c')
-rw-r--r-- | firmware/target/arm/s5l8700/uart-s5l8701.c | 160 |
1 files changed, 160 insertions, 0 deletions
diff --git a/firmware/target/arm/s5l8700/uart-s5l8701.c b/firmware/target/arm/s5l8700/uart-s5l8701.c new file mode 100644 index 0000000000..00c9322e47 --- /dev/null +++ b/firmware/target/arm/s5l8700/uart-s5l8701.c | |||
@@ -0,0 +1,160 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2014 by Cástor Muñoz | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include <stdint.h> | ||
22 | #include <stdbool.h> | ||
23 | |||
24 | #include "config.h" | ||
25 | #include "system.h" | ||
26 | |||
27 | #include "s5l8700.h" | ||
28 | #include "uc870x.h" | ||
29 | |||
30 | |||
31 | /* | ||
32 | * s5l8701 UC870X HW: 3 UARTC, 1 port per UARTC | ||
33 | */ | ||
34 | static struct uartc_port *uartc0_port_l[UARTC0_N_PORTS]; | ||
35 | const struct uartc s5l8701_uartc0 = | ||
36 | { | ||
37 | .id = 0, | ||
38 | .baddr = UARTC0_BASE_ADDR, | ||
39 | .port_off = UARTC0_PORT_OFFSET, | ||
40 | .n_ports = UARTC0_N_PORTS, | ||
41 | .port_l = uartc0_port_l, | ||
42 | }; | ||
43 | |||
44 | /* UARTC1,2 not used on Nano2G */ | ||
45 | #ifndef IPOD_NANO2G | ||
46 | static struct uartc_port *uartc1_port_l[UARTC1_N_PORTS]; | ||
47 | const struct uartc s5l8701_uartc1 = | ||
48 | { | ||
49 | .id = 1, | ||
50 | .baddr = UARTC1_BASE_ADDR, | ||
51 | .port_off = UARTC1_PORT_OFFSET, | ||
52 | .n_ports = UARTC1_N_PORTS, | ||
53 | .port_l = uartc1_port_l, | ||
54 | }; | ||
55 | |||
56 | static struct uartc_port *uartc2_port_l[UARTC2_N_PORTS]; | ||
57 | const struct uartc s5l8701_uartc2 = | ||
58 | { | ||
59 | .id = 2, | ||
60 | .baddr = UARTC2_BASE_ADDR, | ||
61 | .port_off = UARTC2_PORT_OFFSET, | ||
62 | .n_ports = UARTC2_N_PORTS, | ||
63 | .port_l = uartc2_port_l, | ||
64 | }; | ||
65 | #endif | ||
66 | |||
67 | static uint8_t clockgate_uartc[S5L8701_N_UARTC] = { | ||
68 | CLOCKGATE_UARTC0, CLOCKGATE_UARTC1, CLOCKGATE_UARTC2 }; | ||
69 | |||
70 | static int intmsk_uart[S5L8701_N_UARTC] = { | ||
71 | INTMSK_UART0, INTMSK_UART1, INTMSK_UART2 }; | ||
72 | |||
73 | /* | ||
74 | * Device level functions specific to S5L8701 | ||
75 | */ | ||
76 | void uart_target_enable_gpio(int uart_id, int port_id) | ||
77 | { | ||
78 | (void) port_id; | ||
79 | switch (uart_id) { | ||
80 | /* configure UARTx Tx/Rx GPIO ports */ | ||
81 | case 0: | ||
82 | PCON1 = (PCON1 & 0xffffff00) | 0x00000044; | ||
83 | break; | ||
84 | case 1: | ||
85 | case 2: | ||
86 | /* unknown */ | ||
87 | default: | ||
88 | break; | ||
89 | } | ||
90 | } | ||
91 | |||
92 | void uart_target_disable_gpio(int uart_id, int port_id) | ||
93 | { | ||
94 | (void) port_id; | ||
95 | switch (uart_id) { | ||
96 | /* configure minimal power consumption */ | ||
97 | case 0: | ||
98 | PCON1 = (PCON1 & 0xffffff00) | 0x00000011; | ||
99 | break; | ||
100 | case 1: | ||
101 | case 2: | ||
102 | default: | ||
103 | break; | ||
104 | } | ||
105 | } | ||
106 | |||
107 | void uart_target_enable_irq(int uart_id, int port_id) | ||
108 | { | ||
109 | (void) port_id; | ||
110 | INTMSK |= intmsk_uart[uart_id]; | ||
111 | } | ||
112 | |||
113 | void uart_target_disable_irq(int uart_id, int port_id) | ||
114 | { | ||
115 | (void) port_id; | ||
116 | INTMSK &= ~intmsk_uart[uart_id]; | ||
117 | } | ||
118 | |||
119 | void uart_target_clear_irq(int uart_id, int port_id) | ||
120 | { | ||
121 | (void) port_id; | ||
122 | SRCPND |= intmsk_uart[uart_id]; | ||
123 | } | ||
124 | |||
125 | void uart_target_enable_clocks(int uart_id) | ||
126 | { | ||
127 | PWRCON &= ~(1 << clockgate_uartc[uart_id]); | ||
128 | } | ||
129 | |||
130 | void uart_target_disable_clocks(int uart_id) | ||
131 | { | ||
132 | PWRCON |= (1 << clockgate_uartc[uart_id]); | ||
133 | } | ||
134 | |||
135 | /* | ||
136 | * ISRs | ||
137 | */ | ||
138 | void ICODE_ATTR INT_UART0(void) | ||
139 | { | ||
140 | uartc_callback(&s5l8701_uartc0, 0); | ||
141 | } | ||
142 | |||
143 | /* UARTC1,2 not used on Nano2G */ | ||
144 | #ifndef IPOD_NANO2G | ||
145 | void ICODE_ATTR INT_UART1(void) | ||
146 | { | ||
147 | uartc_callback(&s5l8701_uartc1, 0); | ||
148 | } | ||
149 | |||
150 | void ICODE_ATTR INT_UART2(void) | ||
151 | { | ||
152 | uartc_callback(&s5l8701_uartc2, 0); | ||
153 | } | ||
154 | #endif | ||
155 | |||
156 | /* Main init */ | ||
157 | void uart_init(void) | ||
158 | { | ||
159 | uartc_open(&s5l8701_uartc0); | ||
160 | } | ||