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authorRafaël Carré <rafael.carre@gmail.com>2010-03-25 23:01:56 +0000
committerRafaël Carré <rafael.carre@gmail.com>2010-03-25 23:01:56 +0000
commita8d1690ffec4a67fdcb0836fd91989fd1dbf5a7a (patch)
treeffd2e99e3a61d03641e663c5574ed0adf30d8df0 /firmware/target/arm/s5l8700/system-target.h
parent43bc2e586ae3194541bc5a835803750fcd2c1c0d (diff)
downloadrockbox-a8d1690ffec4a67fdcb0836fd91989fd1dbf5a7a.tar.gz
rockbox-a8d1690ffec4a67fdcb0836fd91989fd1dbf5a7a.zip
Make storage alignement use cache alignement macros
Introduce STORAGE_ALIGN_DOWN, STORAGE_PAD (using new CACHE_PAD) and STORAGE_OVERLAP (using new CACHE_OVERLAP), make them useful only when PROC_NEEDS_CACHEALIGN and STORAGE_NEEDS_ALIGN are defined Modify PP and nano2g system-target.h accordingly git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25336 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/s5l8700/system-target.h')
-rw-r--r--firmware/target/arm/s5l8700/system-target.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h
index 81e5c7f7fd..c531344b64 100644
--- a/firmware/target/arm/s5l8700/system-target.h
+++ b/firmware/target/arm/s5l8700/system-target.h
@@ -29,6 +29,11 @@
29#define CPUFREQ_NORMAL 47923200 29#define CPUFREQ_NORMAL 47923200
30#define CPUFREQ_MAX 191692800 30#define CPUFREQ_MAX 191692800
31 31
32/* DMA engine needs aligned addresses */
33#define PROC_NEEDS_CACHEALIGN
34#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
35#define NEEDS_STORAGE_ALIGN
36
32#define inl(a) (*(volatile unsigned long *) (a)) 37#define inl(a) (*(volatile unsigned long *) (a))
33#define outl(a,b) (*(volatile unsigned long *) (b) = (a)) 38#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
34#define inb(a) (*(volatile unsigned char *) (a)) 39#define inb(a) (*(volatile unsigned char *) (a))