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author | Michael Sevakis <jethead71@rockbox.org> | 2008-03-31 01:29:50 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2008-03-31 01:29:50 +0000 |
commit | a65406e3f48daed80f4d1b8627fae38a683fecb6 (patch) | |
tree | 0ba581f99dfcf18727fa05152b5a8b25fae86410 /firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c | |
parent | 241fd0fbdb218518cabbc6430dc0159b348549bc (diff) | |
download | rockbox-a65406e3f48daed80f4d1b8627fae38a683fecb6.tar.gz rockbox-a65406e3f48daed80f4d1b8627fae38a683fecb6.zip |
meg-fx: It's important to make sure certain interrupt-related registers have bits changed atomically.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16894 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c')
-rw-r--r-- | firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c b/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c index 7e4e608e15..c5d23a3673 100644 --- a/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c +++ b/firmware/target/arm/s3c2440/gigabeat-fx/i2c-meg-fx.c | |||
@@ -41,7 +41,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
41 | mutex_lock(&i2c_mtx); | 41 | mutex_lock(&i2c_mtx); |
42 | 42 | ||
43 | /* Turn on I2C clock */ | 43 | /* Turn on I2C clock */ |
44 | CLKCON |= (1 << 16); | 44 | s3c_regset(&CLKCON, 1 << 16); |
45 | 45 | ||
46 | /* Set mode to master transmitter and enable lines */ | 46 | /* Set mode to master transmitter and enable lines */ |
47 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; | 47 | IICSTAT = I2C_MODE_MASTER | I2C_MODE_TX | I2C_RXTX_ENB; |
@@ -74,7 +74,7 @@ void i2c_write(int addr, const unsigned char *buf, int count) | |||
74 | IICSTAT = 0; | 74 | IICSTAT = 0; |
75 | 75 | ||
76 | /* Turn off I2C clock */ | 76 | /* Turn off I2C clock */ |
77 | CLKCON &= ~(1 << 16); | 77 | s3c_regclr(&CLKCON, 1 << 16); |
78 | 78 | ||
79 | mutex_unlock(&i2c_mtx); | 79 | mutex_unlock(&i2c_mtx); |
80 | } | 80 | } |
@@ -90,11 +90,11 @@ void i2c_init(void) | |||
90 | INTPND = IIC_MASK; | 90 | INTPND = IIC_MASK; |
91 | 91 | ||
92 | /* Enable i2c interrupt in controller */ | 92 | /* Enable i2c interrupt in controller */ |
93 | INTMOD &= ~IIC_MASK; | 93 | s3c_regclr(&INTMOD, IIC_MASK); |
94 | INTMSK &= ~IIC_MASK; | 94 | s3c_regclr(&INTMSK, IIC_MASK); |
95 | 95 | ||
96 | /* Turn on I2C clock */ | 96 | /* Turn on I2C clock */ |
97 | CLKCON |= (1 << 16); | 97 | s3c_regset(&CLKCON, 1 << 16); |
98 | 98 | ||
99 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ | 99 | /* Set GPE15 (IICSDA) and GPE14 (IICSCL) to IIC */ |
100 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | | 100 | GPECON = (GPECON & ~((3 << 30) | (3 << 28))) | |
@@ -108,7 +108,7 @@ void i2c_init(void) | |||
108 | IICLC = (0 << 0); | 108 | IICLC = (0 << 0); |
109 | 109 | ||
110 | /* Turn off I2C clock */ | 110 | /* Turn off I2C clock */ |
111 | CLKCON &= ~(1 << 16); | 111 | s3c_regclr(&CLKCON, 1 << 16); |
112 | } | 112 | } |
113 | 113 | ||
114 | void IIC(void) | 114 | void IIC(void) |