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| author | Andrew Ryabinin <ryabinin.a.a@gmail.com> | 2014-11-29 17:06:35 +0300 |
|---|---|---|
| committer | Andrew Ryabinin <ryabinin.a.a@gmail.com> | 2014-11-29 21:00:11 +0300 |
| commit | 8618f2c227e7daed2d1dd566090c2c4588533470 (patch) | |
| tree | 2225821258966d4076c00b1ee8afc9523f8c0d3e /firmware/target/arm/rk27xx/system-target.h | |
| parent | d1fcfe950a70ddbdd97164832cdb83ef2cc7f23a (diff) | |
| download | rockbox-8618f2c227e7daed2d1dd566090c2c4588533470.tar.gz rockbox-8618f2c227e7daed2d1dd566090c2c4588533470.zip | |
rk27xx: sd: properly align buffer used for DMA transfers.
Commit 7d1a47cf ("Rewrite filesystem code (WIP)") exposed
bug in rk27xx sd driver. Buffer passed to sd_read/write_sectors()
doesn't has to be cacheline aligned. DMA transfers on
unaligned buffers is quiet dangerous thing.
Make sure that the buffer is aligned to cacheline size,
If not use a temporary aligned buffer for DMA transfer.
Change-Id: I91420f2b8d58159c80c3f15f4b35e88ea0dfd14c
Diffstat (limited to 'firmware/target/arm/rk27xx/system-target.h')
| -rw-r--r-- | firmware/target/arm/rk27xx/system-target.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/firmware/target/arm/rk27xx/system-target.h b/firmware/target/arm/rk27xx/system-target.h index 8a705dd77a..a5b27cc6b2 100644 --- a/firmware/target/arm/rk27xx/system-target.h +++ b/firmware/target/arm/rk27xx/system-target.h | |||
| @@ -52,4 +52,6 @@ void commit_discard_idcache(void); | |||
| 52 | #define CPUFREQ_NORMAL 50000000 | 52 | #define CPUFREQ_NORMAL 50000000 |
| 53 | #define CPUFREQ_MAX 200000000 | 53 | #define CPUFREQ_MAX 200000000 |
| 54 | 54 | ||
| 55 | #define STORAGE_WANTS_ALIGN | ||
| 56 | |||
| 55 | #endif /* SYSTEM_TARGET_H */ | 57 | #endif /* SYSTEM_TARGET_H */ |