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author | Marcin Bukat <marcin.bukat@gmail.com> | 2012-08-06 20:22:57 +0200 |
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committer | Marcin Bukat <marcin.bukat@gmail.com> | 2012-08-30 13:50:36 +0200 |
commit | 722e24a76ac7a2c550f8428c5762f40dd9313d91 (patch) | |
tree | b1398f2740c77b20973099c48db4d846bfd84a99 /firmware/target/arm/rk27xx/system-rk27xx.c | |
parent | 417da66bb3e02849b8a63213818f2fed1d8354fb (diff) | |
download | rockbox-722e24a76ac7a2c550f8428c5762f40dd9313d91.tar.gz rockbox-722e24a76ac7a2c550f8428c5762f40dd9313d91.zip |
rk27xx: implement frequency scalling
Implemented scheme:
ARM AHB APB
Normal 50 50 50 MHz
Max 200 100 50 MHz
Frequency scaling is disabled on rk27generic due to too
slow lcd updates when running with 50MHz AHB.
battery_bench shows ~1h runtime improvement on hifiman.
Change-Id: I2c6f8acf6d4570c4e14f5bcc72280b51ce13c408
Diffstat (limited to 'firmware/target/arm/rk27xx/system-rk27xx.c')
-rw-r--r-- | firmware/target/arm/rk27xx/system-rk27xx.c | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/firmware/target/arm/rk27xx/system-rk27xx.c b/firmware/target/arm/rk27xx/system-rk27xx.c index 1b4505541f..8c75deef07 100644 --- a/firmware/target/arm/rk27xx/system-rk27xx.c +++ b/firmware/target/arm/rk27xx/system-rk27xx.c | |||
@@ -231,3 +231,58 @@ void commit_discard_dcache_range (const void *base, unsigned int size) | |||
231 | opcode += 32; | 231 | opcode += 32; |
232 | } | 232 | } |
233 | } | 233 | } |
234 | |||
235 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | ||
236 | static inline void set_sdram_timing(int ahb_freq) | ||
237 | { | ||
238 | MCSDR_T_REF = (125*ahb_freq/1000000) >> 3; | ||
239 | MCSDR_T_RFC = (64*ahb_freq/1000000)/1000; | ||
240 | } | ||
241 | |||
242 | void set_cpu_frequency(long frequency) | ||
243 | { | ||
244 | if (cpu_frequency == frequency) | ||
245 | return; | ||
246 | |||
247 | set_sdram_timing(12000000); | ||
248 | |||
249 | if (frequency == CPUFREQ_MAX) | ||
250 | { | ||
251 | /* PLL set to 200 Mhz | ||
252 | * PLL:ARM = 1:1 | ||
253 | * ARM:AHB = 2:1 | ||
254 | * AHB:APB = 2:1 | ||
255 | */ | ||
256 | SCU_DIVCON1 = (SCU_DIVCON1 &~ 0x1f) | (1<<3)|1; | ||
257 | SCU_PLLCON1 = ((1<<24)|(1<<23)|(5<<16)|(49<<4)); /*((24/6)*50)/1*/ | ||
258 | |||
259 | /* wait for PLL lock ~0.3 ms */ | ||
260 | while (!(SCU_STATUS & 1)); | ||
261 | |||
262 | /* leave SLOW mode */ | ||
263 | SCU_DIVCON1 &= ~1; | ||
264 | |||
265 | set_sdram_timing(CPUFREQ_MAX/2); | ||
266 | } | ||
267 | else | ||
268 | { | ||
269 | /* PLL set to 100 MHz | ||
270 | * PLL:ARM = 2:1 | ||
271 | * ARM:AHB = 1:1 | ||
272 | * AHB:APB = 1:1 | ||
273 | */ | ||
274 | SCU_DIVCON1 = (SCU_DIVCON1 & ~0x1f) | (1<<2)|1; | ||
275 | SCU_PLLCON1 = ((1<<24)|(1<<23)|(5<<16)|(49<<4)|(1<<1)); /*((24/6)*50)/2*/ | ||
276 | |||
277 | /* wait for PLL lock ~0.3 ms */ | ||
278 | while (!(SCU_STATUS & 1)); | ||
279 | |||
280 | /* leave SLOW mode */ | ||
281 | SCU_DIVCON1 &= ~1; | ||
282 | |||
283 | set_sdram_timing(CPUFREQ_NORMAL); | ||
284 | } | ||
285 | |||
286 | cpu_frequency = frequency; | ||
287 | } | ||
288 | #endif | ||