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author | Marcin Bukat <marcin.bukat@gmail.com> | 2012-12-17 08:44:09 +0100 |
---|---|---|
committer | Marcin Bukat <marcin.bukat@gmail.com> | 2013-01-10 20:23:41 +0100 |
commit | 2b6dfdb34e8e750528b91276c504f1664dfdef4c (patch) | |
tree | 17dd8a0b5cbdc18600e59c16a076f2580948d88c /firmware/target/arm/rk27xx/system-rk27xx.c | |
parent | 1fa406dc216cbbabd9f17df6312abf205976276f (diff) | |
download | rockbox-2b6dfdb34e8e750528b91276c504f1664dfdef4c.tar.gz rockbox-2b6dfdb34e8e750528b91276c504f1664dfdef4c.zip |
rk27xx: substitute magic constants with meaningful names for clock gating
Change-Id: I6c66c7496db3db78e5c959414464826134dbe200
Diffstat (limited to 'firmware/target/arm/rk27xx/system-rk27xx.c')
-rw-r--r-- | firmware/target/arm/rk27xx/system-rk27xx.c | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/firmware/target/arm/rk27xx/system-rk27xx.c b/firmware/target/arm/rk27xx/system-rk27xx.c index d264476328..327ef73422 100644 --- a/firmware/target/arm/rk27xx/system-rk27xx.c +++ b/firmware/target/arm/rk27xx/system-rk27xx.c | |||
@@ -130,20 +130,20 @@ void system_init(void) | |||
130 | MCSDR_T_RCD = 1; /* active to RD/WR delay */ | 130 | MCSDR_T_RCD = 1; /* active to RD/WR delay */ |
131 | 131 | ||
132 | /* turn off clock for unused modules */ | 132 | /* turn off clock for unused modules */ |
133 | SCU_CLKCFG |= (1<<31) | /* WDT pclk */ | 133 | SCU_CLKCFG |= CLKCFG_WDT | /* WDT pclk */ |
134 | (1<<30) | /* RTC pclk */ | 134 | CLKCFG_RTC | /* RTC pclk */ |
135 | (1<<26) | /* HS_ADC clock */ | 135 | CLKCFG_HSADC | /* HS_ADC clock */ |
136 | (1<<25) | /* HS_ADC HCLK */ | 136 | CLKCFG_HCLK_HSADC | /* HS_ADC HCLK */ |
137 | (1<<21) | /* SPI clock */ | 137 | CLKCFG_SPI | /* SPI clock */ |
138 | (1<<19) | /* UART1 clock */ | 138 | CLKCFG_UART1 | /* UART1 clock */ |
139 | (1<<18) | /* UART0 clock */ | 139 | CLKCFG_UART0 | /* UART0 clock */ |
140 | (1<<15) | /* VIP clock */ | 140 | CLKCFG_VIP | /* VIP clock */ |
141 | (1<<14) | /* VIP HCLK */ | 141 | CLKCFG_HCLK_VIP | /* VIP HCLK */ |
142 | (1<<13) | /* LCDC clock */ | 142 | CLKCFG_LCDC | /* LCDC clock */ |
143 | (1<<9) | /* NAND HCLK */ | 143 | CLKCFG_NAND | /* NAND HCLK */ |
144 | (1<<5) | /* USB host HCLK */ | 144 | CLKCFG_UHC | /* USB host HCLK */ |
145 | (1<<1) | /* DSP clock */ | 145 | CLKCFG_DSP | /* DSP clock */ |
146 | (1<<0); /* OTP clock (dunno what it is */ | 146 | CLKCFG_OTP; /* OTP clock (dunno what it is */ |
147 | 147 | ||
148 | /* turn off DSP pll */ | 148 | /* turn off DSP pll */ |
149 | SCU_PLLCON2 |= (1<<22); | 149 | SCU_PLLCON2 |= (1<<22); |
@@ -157,7 +157,7 @@ void system_init(void) | |||
157 | void system_reboot(void) | 157 | void system_reboot(void) |
158 | { | 158 | { |
159 | /* use Watchdog to reset */ | 159 | /* use Watchdog to reset */ |
160 | SCU_CLKCFG &= ~(1<<31); | 160 | SCU_CLKCFG &= ~CLKCFG_WDT; |
161 | WDTLR = 1; | 161 | WDTLR = 1; |
162 | WDTCON = (1<<4) | (1<<3); | 162 | WDTCON = (1<<4) | (1<<3); |
163 | 163 | ||