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author | Marcin Bukat <marcin.bukat@gmail.com> | 2011-05-30 21:10:37 +0000 |
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committer | Marcin Bukat <marcin.bukat@gmail.com> | 2011-05-30 21:10:37 +0000 |
commit | 976a1699da373f01dabc9353b34aef261ebf740f (patch) | |
tree | 5f1649ceb51d603471e6b1cf5dcb5192626897d6 /firmware/target/arm/rk27xx/crt0.S | |
parent | 8a5a2b82fd2d35e3eb7afa8f0dc875e3874988bb (diff) | |
download | rockbox-976a1699da373f01dabc9353b34aef261ebf740f.tar.gz rockbox-976a1699da373f01dabc9353b34aef261ebf740f.zip |
Rockchip rk27xx port initial commit. This is still work in progress.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29935 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/rk27xx/crt0.S')
-rw-r--r-- | firmware/target/arm/rk27xx/crt0.S | 209 |
1 files changed, 209 insertions, 0 deletions
diff --git a/firmware/target/arm/rk27xx/crt0.S b/firmware/target/arm/rk27xx/crt0.S new file mode 100644 index 0000000000..032c637458 --- /dev/null +++ b/firmware/target/arm/rk27xx/crt0.S | |||
@@ -0,0 +1,209 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id: crt0.S 18776 2008-10-11 18:32:17Z gevaerts $ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Marcoen Hirschberg | ||
11 | * Copyright (C) 2008 by Denes Balatoni | ||
12 | * Copyright (C) 2010 by Marcin Bukat | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #define ASM | ||
24 | #include "config.h" | ||
25 | #include "cpu.h" | ||
26 | |||
27 | .section .intvect,"ax",%progbits | ||
28 | .global start | ||
29 | .global _newstart | ||
30 | /* Exception vectors */ | ||
31 | start: | ||
32 | b _newstart | ||
33 | ldr pc, =undef_instr_handler | ||
34 | ldr pc, =software_int_handler | ||
35 | ldr pc, =prefetch_abort_handler | ||
36 | ldr pc, =data_abort_handler | ||
37 | ldr pc, =reserved_handler | ||
38 | ldr pc, =irq_handler | ||
39 | ldr pc, =fiq_handler | ||
40 | .ltorg | ||
41 | _newstart: | ||
42 | ldr pc, =newstart2 | ||
43 | .section .init.text,"ax",%progbits | ||
44 | newstart2: | ||
45 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ | ||
46 | |||
47 | mov r0, #0x18000000 | ||
48 | add r0, r0, #0x1c000 | ||
49 | |||
50 | /* setup ARM core freq = 200MHz */ | ||
51 | /* AHB bus freq (HCLK) = 100MHz */ | ||
52 | /* APB bus freq (PCLK) = 50MHz */ | ||
53 | ldr r1, [r0,#0x14] /* SCU_DIVCON1 */ | ||
54 | orr r1, #9 /* ARM slow mode, HCLK:PCLK = 2:1 */ | ||
55 | str r1, [r0,#0x14] | ||
56 | |||
57 | ldr r1,=0x01970c70 /* (1<<24) | (1<<23) | (23<<16) | (199<<4) */ | ||
58 | str r1, [r0,#0x08] | ||
59 | |||
60 | ldr r2,=0x40000 | ||
61 | 1: | ||
62 | ldr r1, [r0,#0x2c] /* SCU_STATUS */ | ||
63 | tst r1, #1 /* ARM pll lock */ | ||
64 | bne 1f | ||
65 | subs r2, #1 | ||
66 | bne 1b | ||
67 | 1: | ||
68 | ldr r1, [r0,#0x14] /* SCU_DIVCON1 */ | ||
69 | bic r1, #5 /* leave ARM slow mode, ARMclk:HCLK = 2:1 */ | ||
70 | str r1, [r0,#0x14] | ||
71 | |||
72 | #if defined(BOOTLOADER) | ||
73 | /* remap iram to 0x00000000 */ | ||
74 | ldr r1,=0xdeadbeef | ||
75 | str r1, [r0, #4] | ||
76 | #endif | ||
77 | |||
78 | #if 0 | ||
79 | /* setup caches */ | ||
80 | ldr r0, =0xefff0000 /* cache controler base address */ | ||
81 | ldrh r1, [r0] | ||
82 | strh r1, [r0] /* global cache disable */ | ||
83 | |||
84 | /* setup uncached regions */ | ||
85 | mov r1, #0x18000000 | ||
86 | orr r1, r1, #0xfe | ||
87 | str r1, [r0,#0x10] /* MemMapA BUS0IP, 32MB */ | ||
88 | str r1, [r0,#0x14] /* MemMapB BUS0IP, 32MB */ | ||
89 | mov r1, #0x30000000 | ||
90 | orr r1, r1, #0xfe | ||
91 | str r1, [r0,#0x18] /* MemMapC DSPMEM, 32MB */ | ||
92 | mov r1, #0xee000000 /* 0xefff0000 & 0xfe000000 */ | ||
93 | orr r1, r1, #0xfe | ||
94 | str r1, [r0,#0x1c] /* MemMapD cache controller, 32MB */ | ||
95 | |||
96 | mov r1, #2 /* invalidate way opcode */ | ||
97 | str r1, [r0,#4] /* invalidate way0 */ | ||
98 | 1: | ||
99 | ldr r2, [r0,#4] | ||
100 | tst r2, #3 | ||
101 | bne 1b /* wait for invalidate to complete */ | ||
102 | |||
103 | orr r1, r1, #0x80000000 | ||
104 | str r1, [r0,#4] /* invalidate way1 */ | ||
105 | 1: | ||
106 | ldr r2, [r0,#4] | ||
107 | tst r2, #3 | ||
108 | bne 1b /* wait for invalidate to complete */ | ||
109 | |||
110 | ldr r1, [r0] | ||
111 | orr r1, r1, #0x80000000 | ||
112 | str r1, [r0] /* global cache enable */ | ||
113 | #endif | ||
114 | |||
115 | /* Copy interrupt vectors to iram */ | ||
116 | ldr r2, =_intvectstart | ||
117 | ldr r3, =_intvectend | ||
118 | ldr r4, =_intvectcopy | ||
119 | 1: | ||
120 | cmp r3, r2 | ||
121 | ldrhi r1, [r4], #4 | ||
122 | strhi r1, [r2], #4 | ||
123 | bhi 1b | ||
124 | |||
125 | /* Initialise bss section to zero */ | ||
126 | ldr r2, =_edata | ||
127 | ldr r3, =_end | ||
128 | mov r4, #0 | ||
129 | 1: | ||
130 | cmp r3, r2 | ||
131 | strhi r4, [r2], #4 | ||
132 | bhi 1b | ||
133 | |||
134 | #ifndef BOOTLOADER | ||
135 | /* Copy icode and data to ram */ | ||
136 | ldr r2, =_iramstart | ||
137 | ldr r3, =_iramend | ||
138 | ldr r4, =_iramcopy | ||
139 | 1: | ||
140 | cmp r3, r2 | ||
141 | ldrhi r1, [r4], #4 | ||
142 | strhi r1, [r2], #4 | ||
143 | bhi 1b | ||
144 | |||
145 | /* Initialise ibss section to zero */ | ||
146 | ldr r2, =_iedata | ||
147 | ldr r3, =_iend | ||
148 | mov r4, #0 | ||
149 | 1: | ||
150 | cmp r3, r2 | ||
151 | strhi r4, [r2], #4 | ||
152 | bhi 1b | ||
153 | #endif | ||
154 | |||
155 | /* Set up some stack and munge it with 0xdeadbeef */ | ||
156 | ldr sp, =stackend | ||
157 | ldr r2, =stackbegin | ||
158 | ldr r3, =0xdeadbeef | ||
159 | 1: | ||
160 | cmp sp, r2 | ||
161 | strhi r3, [r2], #4 | ||
162 | bhi 1b | ||
163 | |||
164 | /* Set up stack for IRQ mode */ | ||
165 | msr cpsr_c, #0xd2 | ||
166 | ldr sp, =_irqstackend | ||
167 | |||
168 | /* Set up stack for FIQ mode */ | ||
169 | msr cpsr_c, #0xd1 | ||
170 | ldr sp, =_fiqstackend | ||
171 | |||
172 | /* Let abort and undefined modes use IRQ stack */ | ||
173 | msr cpsr_c, #0xd7 | ||
174 | ldr sp, =_irqstackend | ||
175 | msr cpsr_c, #0xdb | ||
176 | ldr sp, =_irqstackend | ||
177 | |||
178 | /* Switch back to supervisor mode */ | ||
179 | msr cpsr_c, #0xd3 | ||
180 | |||
181 | bl main | ||
182 | |||
183 | .text | ||
184 | /* .global UIE*/ | ||
185 | |||
186 | /* All illegal exceptions call into UIE with exception address as first | ||
187 | * parameter. This is calculated differently depending on which exception | ||
188 | * we're in. Second parameter is exception number, used for a string lookup | ||
189 | * in UIE. */ | ||
190 | undef_instr_handler: | ||
191 | sub r0, lr, #4 | ||
192 | mov r1, #0 | ||
193 | b UIE | ||
194 | |||
195 | /* We run supervisor mode most of the time, and should never see a software | ||
196 | * exception being thrown. Perhaps make it illegal and call UIE? */ | ||
197 | software_int_handler: | ||
198 | reserved_handler: | ||
199 | movs pc, lr | ||
200 | |||
201 | prefetch_abort_handler: | ||
202 | sub r0, lr, #4 | ||
203 | mov r1, #1 | ||
204 | b UIE | ||
205 | |||
206 | data_abort_handler: | ||
207 | sub r0, lr, #8 | ||
208 | mov r1, #2 | ||
209 | b UIE | ||