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author | Michael Sevakis <jethead71@rockbox.org> | 2014-08-08 01:39:29 -0400 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2014-08-08 01:59:59 -0400 |
commit | 981d028c09d10ed867f2f955f58d60b753c64f29 (patch) | |
tree | 0dab835a14c5cb3e740be4e46be93c42aec76bc5 /firmware/target/arm/pp | |
parent | 53d9f2e6a7564e487bdac87f6e28c662e8407458 (diff) | |
download | rockbox-981d028c09d10ed867f2f955f58d60b753c64f29.tar.gz rockbox-981d028c09d10ed867f2f955f58d60b753c64f29.zip |
Do some kernel cleanup
* Seal away private thread and kernel definitions and declarations
into the internal headers in order to better hide internal structure.
* Add a thread-common.c file that keeps shared functions together.
List functions aren't messed with since that's about to be changed to
different ones.
* It is necessary to modify some ARM/PP stuff since GCC was complaining
about constant pool distance and I would rather not force dump it. Just
bl the cache calls in the startup and exit code and let it use veneers
if it must.
* Clean up redundant #includes in relevant areas and reorganize them.
* Expunge useless and dangerous stuff like remove_thread().
Change-Id: I6e22932fad61a9fac30fd1363c071074ee7ab382
Diffstat (limited to 'firmware/target/arm/pp')
-rw-r--r-- | firmware/target/arm/pp/thread-pp.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/firmware/target/arm/pp/thread-pp.c b/firmware/target/arm/pp/thread-pp.c index ed4bdbeac1..b2e7fb018d 100644 --- a/firmware/target/arm/pp/thread-pp.c +++ b/firmware/target/arm/pp/thread-pp.c | |||
@@ -45,7 +45,7 @@ extern uintptr_t cpu_idlestackbegin[]; | |||
45 | extern uintptr_t cpu_idlestackend[]; | 45 | extern uintptr_t cpu_idlestackend[]; |
46 | extern uintptr_t cop_idlestackbegin[]; | 46 | extern uintptr_t cop_idlestackbegin[]; |
47 | extern uintptr_t cop_idlestackend[]; | 47 | extern uintptr_t cop_idlestackend[]; |
48 | static uintptr_t * const idle_stacks[NUM_CORES] = | 48 | uintptr_t * const idle_stacks[NUM_CORES] = |
49 | { | 49 | { |
50 | [CPU] = cpu_idlestackbegin, | 50 | [CPU] = cpu_idlestackbegin, |
51 | [COP] = cop_idlestackbegin | 51 | [COP] = cop_idlestackbegin |
@@ -92,9 +92,7 @@ static inline void NORETURN_ATTR __attribute__((always_inline)) | |||
92 | { | 92 | { |
93 | asm volatile ( | 93 | asm volatile ( |
94 | "cmp %1, #0 \n" /* CPU? */ | 94 | "cmp %1, #0 \n" /* CPU? */ |
95 | "ldrne r0, =commit_dcache \n" /* No? write back data */ | 95 | "blne commit_dcache \n" |
96 | "movne lr, pc \n" | ||
97 | "bxne r0 \n" | ||
98 | "mov r0, %0 \n" /* copy thread parameter */ | 96 | "mov r0, %0 \n" /* copy thread parameter */ |
99 | "mov sp, %2 \n" /* switch to idle stack */ | 97 | "mov sp, %2 \n" /* switch to idle stack */ |
100 | "bl thread_final_exit_do \n" /* finish removal */ | 98 | "bl thread_final_exit_do \n" /* finish removal */ |
@@ -163,9 +161,7 @@ static void __attribute__((naked)) | |||
163 | "ldr sp, [r0, #32] \n" /* Reload original sp from context structure */ | 161 | "ldr sp, [r0, #32] \n" /* Reload original sp from context structure */ |
164 | "mov r1, #0 \n" /* Clear start address */ | 162 | "mov r1, #0 \n" /* Clear start address */ |
165 | "str r1, [r0, #40] \n" | 163 | "str r1, [r0, #40] \n" |
166 | "ldr r0, =commit_discard_idcache \n" /* Invalidate new core's cache */ | 164 | "bl commit_discard_idcache \n" /* Invalidate new core's cache */ |
167 | "mov lr, pc \n" | ||
168 | "bx r0 \n" | ||
169 | "ldmfd sp!, { r4-r11, pc } \n" /* Restore non-volatile context to new core and return */ | 165 | "ldmfd sp!, { r4-r11, pc } \n" /* Restore non-volatile context to new core and return */ |
170 | : : "i"(IDLE_STACK_WORDS) | 166 | : : "i"(IDLE_STACK_WORDS) |
171 | ); | 167 | ); |