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author | Rafaël Carré <rafael.carre@gmail.com> | 2012-01-03 04:39:56 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2012-01-03 04:39:56 +0000 |
commit | 5cf79723ecb9a22de432d169ce65eb19aa651e8a (patch) | |
tree | 8e646c327a144a6630f260fc64f183a9bb80b4df /firmware/target/arm/pp/system-pp502x.c | |
parent | bbe5845f04433846c553579d70310bef8efd0f50 (diff) | |
download | rockbox-5cf79723ecb9a22de432d169ce65eb19aa651e8a.tar.gz rockbox-5cf79723ecb9a22de432d169ce65eb19aa651e8a.zip |
move PP specific files to pp/
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31533 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/pp/system-pp502x.c')
-rw-r--r-- | firmware/target/arm/pp/system-pp502x.c | 607 |
1 files changed, 607 insertions, 0 deletions
diff --git a/firmware/target/arm/pp/system-pp502x.c b/firmware/target/arm/pp/system-pp502x.c new file mode 100644 index 0000000000..847e8a462e --- /dev/null +++ b/firmware/target/arm/pp/system-pp502x.c | |||
@@ -0,0 +1,607 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2002 by Alan Korr | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "system.h" | ||
22 | #include "thread.h" | ||
23 | #include "i2s.h" | ||
24 | #include "i2c-pp.h" | ||
25 | #include "as3514.h" | ||
26 | #ifdef HAVE_HOTSWAP | ||
27 | #include "sd-pp-target.h" | ||
28 | #endif | ||
29 | #include "button-target.h" | ||
30 | #include "usb_drv.h" | ||
31 | #ifdef HAVE_REMOTE_LCD | ||
32 | #include "lcd-remote-target.h" | ||
33 | #endif | ||
34 | |||
35 | #if !defined(BOOTLOADER) || defined(HAVE_BOOTLOADER_USB_MODE) | ||
36 | extern void TIMER1(void); | ||
37 | extern void TIMER2(void); | ||
38 | extern void SERIAL0(void); | ||
39 | |||
40 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | ||
41 | static struct corelock cpufreq_cl SHAREDBSS_ATTR; | ||
42 | #endif | ||
43 | |||
44 | #if defined(IPOD_VIDEO) && !defined(BOOTLOADER) | ||
45 | unsigned char probed_ramsize; | ||
46 | #endif | ||
47 | |||
48 | void __attribute__((interrupt("IRQ"))) irq_handler(void) | ||
49 | { | ||
50 | if(CURRENT_CORE == CPU) | ||
51 | { | ||
52 | if (CPU_INT_STAT & TIMER1_MASK) { | ||
53 | TIMER1(); | ||
54 | } | ||
55 | else if (CPU_INT_STAT & TIMER2_MASK) { | ||
56 | TIMER2(); | ||
57 | } | ||
58 | #ifdef HAVE_USBSTACK | ||
59 | /* Rather high priority - place near front */ | ||
60 | else if (CPU_INT_STAT & USB_MASK) { | ||
61 | usb_drv_int(); | ||
62 | } | ||
63 | #endif | ||
64 | #if defined(IPOD_MINI) /* Mini 1st gen only, mini 2nd gen uses iPod 4G code */ | ||
65 | else if (CPU_HI_INT_STAT & GPIO0_MASK) { | ||
66 | if ((GPIOA_INT_STAT & 0x3f) || (GPIOB_INT_STAT & 0x30)) | ||
67 | ipod_mini_button_int(); | ||
68 | if (GPIOC_INT_STAT & 0x02) | ||
69 | firewire_insert_int(); | ||
70 | if (GPIOD_INT_STAT & 0x08) | ||
71 | usb_insert_int(); | ||
72 | } | ||
73 | /* end IPOD_MINI */ | ||
74 | #elif CONFIG_KEYPAD == IPOD_4G_PAD /* except Mini 1st gen, handled above */ | ||
75 | else if (CPU_HI_INT_STAT & I2C_MASK) { | ||
76 | ipod_4g_button_int(); | ||
77 | } | ||
78 | #if defined(IPOD_COLOR) || defined(IPOD_MINI2G) || defined(IPOD_4G) | ||
79 | else if (CPU_HI_INT_STAT & GPIO0_MASK) { | ||
80 | if (GPIOC_INT_STAT & 0x02) | ||
81 | firewire_insert_int(); | ||
82 | if (GPIOD_INT_STAT & 0x08) | ||
83 | usb_insert_int(); | ||
84 | } | ||
85 | #elif defined(IPOD_NANO) || defined(IPOD_VIDEO) | ||
86 | else if (CPU_HI_INT_STAT & GPIO2_MASK) { | ||
87 | if (GPIOL_INT_STAT & 0x10) | ||
88 | usb_insert_int(); | ||
89 | } | ||
90 | #endif | ||
91 | /* end CONFIG_KEYPAD == IPOD_4G_PAD */ | ||
92 | #elif defined(IRIVER_H10) || defined(IRIVER_H10_5GB) | ||
93 | else if (CPU_HI_INT_STAT & GPIO2_MASK) { | ||
94 | if (GPIOL_INT_STAT & 0x04) | ||
95 | usb_insert_int(); | ||
96 | } | ||
97 | /* end IRIVER_H10 || IRIVER_H10_5GB */ | ||
98 | #elif defined(SANSA_E200) | ||
99 | else if (CPU_HI_INT_STAT & GPIO0_MASK) { | ||
100 | #ifdef HAVE_HOTSWAP | ||
101 | if (GPIOA_INT_STAT & 0x80) | ||
102 | microsd_int(); | ||
103 | #endif | ||
104 | if (GPIOB_INT_STAT & 0x10) | ||
105 | usb_insert_int(); | ||
106 | } | ||
107 | else if (CPU_HI_INT_STAT & GPIO1_MASK) { | ||
108 | if (GPIOF_INT_STAT & 0xff) | ||
109 | button_int(); | ||
110 | if (GPIOH_INT_STAT & 0xc0) | ||
111 | clickwheel_int(); | ||
112 | } | ||
113 | /* end SANSA_E200 */ | ||
114 | #elif defined(SANSA_C200) | ||
115 | else if (CPU_HI_INT_STAT & GPIO1_MASK) { | ||
116 | if (GPIOH_INT_STAT & 0x02) | ||
117 | usb_insert_int(); | ||
118 | } | ||
119 | #ifdef HAVE_HOTSWAP | ||
120 | else if (CPU_HI_INT_STAT & GPIO2_MASK) { | ||
121 | if (GPIOL_INT_STAT & 0x08) | ||
122 | microsd_int(); | ||
123 | } | ||
124 | #endif | ||
125 | /* end SANSA_C200 */ | ||
126 | #elif defined(MROBE_100) | ||
127 | else if (CPU_HI_INT_STAT & GPIO0_MASK) { | ||
128 | if (GPIOD_INT_STAT & 0x02) | ||
129 | button_int(); | ||
130 | if (GPIOD_INT_STAT & 0x80) | ||
131 | headphones_int(); | ||
132 | |||
133 | } | ||
134 | else if (CPU_HI_INT_STAT & GPIO2_MASK) { | ||
135 | if (GPIOL_INT_STAT & 0x04) | ||
136 | usb_insert_int(); | ||
137 | } | ||
138 | /* end MROBE_100 */ | ||
139 | #elif defined(PHILIPS_SA9200) | ||
140 | else if (CPU_HI_INT_STAT & GPIO0_MASK) { | ||
141 | if (GPIOD_INT_STAT & 0x02) | ||
142 | button_int(); | ||
143 | if (GPIOB_INT_STAT & 0x40) | ||
144 | usb_insert_int(); | ||
145 | } | ||
146 | /* end PHILIPS_SA9200 */ | ||
147 | #elif defined(PHILIPS_HDD1630) || defined(PHILIPS_HDD6330) | ||
148 | else if (CPU_HI_INT_STAT & GPIO0_MASK) { | ||
149 | if (GPIOA_INT_STAT & 0x20) | ||
150 | button_int(); | ||
151 | } | ||
152 | else if (CPU_HI_INT_STAT & GPIO1_MASK) { | ||
153 | if (GPIOE_INT_STAT & 0x04) | ||
154 | usb_insert_int(); | ||
155 | } | ||
156 | /* end PHILIPS_HDD1630 || PHILIPS_HDD6330 */ | ||
157 | #elif defined(SAMSUNG_YH820) || defined(SAMSUNG_YH920) || defined(SAMSUNG_YH925) | ||
158 | else if (CPU_HI_INT_STAT & GPIO0_MASK) { | ||
159 | if (GPIOD_INT_STAT & 0x10) | ||
160 | usb_insert_int(); | ||
161 | } | ||
162 | /* end SAMSUNG_YHxxx */ | ||
163 | #elif defined(PBELL_VIBE500) | ||
164 | else if (CPU_HI_INT_STAT & GPIO0_MASK) { | ||
165 | if (GPIOA_INT_STAT & 0x20) | ||
166 | button_int(); | ||
167 | } | ||
168 | else if (CPU_HI_INT_STAT & GPIO2_MASK) { | ||
169 | if (GPIOL_INT_STAT & 0x04) | ||
170 | usb_insert_int(); | ||
171 | } | ||
172 | /* end PBELL_VIBE500 */ | ||
173 | #endif | ||
174 | #ifdef IPOD_ACCESSORY_PROTOCOL | ||
175 | else if (CPU_HI_INT_STAT & SER0_MASK) { | ||
176 | SERIAL0(); | ||
177 | } | ||
178 | #endif | ||
179 | } else { | ||
180 | if (COP_INT_STAT & TIMER2_MASK) | ||
181 | TIMER2(); | ||
182 | } | ||
183 | } | ||
184 | #endif /* BOOTLOADER || HAVE_BOOTLOADER_USB_MODE */ | ||
185 | |||
186 | #if !defined(BOOTLOADER) || defined(HAVE_BOOTLOADER_USB_MODE) | ||
187 | static void disable_all_interrupts(void) | ||
188 | { | ||
189 | COP_HI_INT_DIS = -1; | ||
190 | CPU_HI_INT_DIS = -1; | ||
191 | HI_INT_FORCED_CLR = -1; | ||
192 | |||
193 | COP_INT_DIS = -1; | ||
194 | CPU_INT_DIS = -1; | ||
195 | INT_FORCED_CLR = -1; | ||
196 | |||
197 | GPIOA_INT_EN = 0; | ||
198 | GPIOB_INT_EN = 0; | ||
199 | GPIOC_INT_EN = 0; | ||
200 | GPIOD_INT_EN = 0; | ||
201 | GPIOE_INT_EN = 0; | ||
202 | GPIOF_INT_EN = 0; | ||
203 | GPIOG_INT_EN = 0; | ||
204 | GPIOH_INT_EN = 0; | ||
205 | GPIOI_INT_EN = 0; | ||
206 | GPIOJ_INT_EN = 0; | ||
207 | GPIOK_INT_EN = 0; | ||
208 | GPIOL_INT_EN = 0; | ||
209 | } | ||
210 | |||
211 | void ICODE_ATTR commit_dcache(void) | ||
212 | { | ||
213 | if (CACHE_CTL & CACHE_CTL_ENABLE) | ||
214 | { | ||
215 | CACHE_OPERATION |= CACHE_OP_FLUSH; | ||
216 | while ((CACHE_CTL & CACHE_CTL_BUSY) != 0); | ||
217 | nop; nop; nop; nop; | ||
218 | } | ||
219 | } | ||
220 | |||
221 | void ICODE_ATTR commit_discard_idcache(void) | ||
222 | { | ||
223 | if (CACHE_CTL & CACHE_CTL_ENABLE) | ||
224 | { | ||
225 | CACHE_OPERATION |= CACHE_OP_FLUSH | CACHE_OP_INVALIDATE; | ||
226 | while ((CACHE_CTL & CACHE_CTL_BUSY) != 0); | ||
227 | nop; nop; nop; nop; | ||
228 | } | ||
229 | } | ||
230 | |||
231 | void commit_discard_dcache(void) __attribute__((alias("commit_discard_idcache"))); | ||
232 | |||
233 | static void init_cache(void) | ||
234 | { | ||
235 | /* Initialising the cache in the iPod bootloader may prevent Rockbox from starting | ||
236 | * depending on the model */ | ||
237 | |||
238 | /* cache init mode */ | ||
239 | CACHE_CTL &= ~(CACHE_CTL_ENABLE | CACHE_CTL_RUN); | ||
240 | CACHE_CTL |= CACHE_CTL_INIT; | ||
241 | |||
242 | #ifndef BOOTLOADER | ||
243 | /* what's this do? */ | ||
244 | CACHE_PRIORITY |= CURRENT_CORE == CPU ? 0x10 : 0x20; | ||
245 | #endif | ||
246 | |||
247 | /* Cache if (addr & mask) >> 16 == (mask & match) >> 16: | ||
248 | * yes: 0x00000000 - 0x03ffffff | ||
249 | * no: 0x04000000 - 0x1fffffff | ||
250 | * yes: 0x20000000 - 0x23ffffff | ||
251 | * no: 0x24000000 - 0x3fffffff | ||
252 | */ | ||
253 | CACHE_MASK = 0x00001c00; | ||
254 | CACHE_OPERATION = 0xfc0; | ||
255 | |||
256 | /* enable cache */ | ||
257 | CACHE_CTL |= CACHE_CTL_INIT | CACHE_CTL_ENABLE | CACHE_CTL_RUN; | ||
258 | nop; nop; nop; nop; | ||
259 | } | ||
260 | #endif /* BOOTLOADER || HAVE_BOOTLOADER_USB_MODE */ | ||
261 | |||
262 | /* We need this for Sansas since we boost the cpu in their bootloader */ | ||
263 | #if !defined(BOOTLOADER) || (defined(SANSA_E200) || defined(SANSA_C200) || \ | ||
264 | defined(PHILIPS_SA9200)) | ||
265 | void scale_suspend_core(bool suspend) ICODE_ATTR; | ||
266 | void scale_suspend_core(bool suspend) | ||
267 | { | ||
268 | unsigned int core = CURRENT_CORE; | ||
269 | IF_COP( unsigned int othercore = 1 - core; ) | ||
270 | static int oldstatus IBSS_ATTR; | ||
271 | |||
272 | if (suspend) | ||
273 | { | ||
274 | oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS); | ||
275 | IF_COP( PROC_CTL(othercore) = 0x40000000; nop; ) | ||
276 | PROC_CTL(core) = 0x48000003; nop; | ||
277 | } | ||
278 | else | ||
279 | { | ||
280 | PROC_CTL(core) = 0x4800001f; nop; | ||
281 | IF_COP( PROC_CTL(othercore) = 0x00000000; nop; ) | ||
282 | restore_interrupt(oldstatus); | ||
283 | } | ||
284 | } | ||
285 | |||
286 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | ||
287 | void set_cpu_frequency(long frequency) ICODE_ATTR; | ||
288 | void set_cpu_frequency(long frequency) | ||
289 | #else | ||
290 | static void pp_set_cpu_frequency(long frequency) | ||
291 | #endif | ||
292 | { | ||
293 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | ||
294 | corelock_lock(&cpufreq_cl); | ||
295 | #endif | ||
296 | |||
297 | switch (frequency) | ||
298 | { | ||
299 | /* Note1: The PP5022 PLL must be run at >= 96MHz | ||
300 | * Bits 20..21 select the post divider (1/2/4/8). | ||
301 | * PP5026 is similar to PP5022 except it doesn't | ||
302 | * have this limitation (and the post divider?) | ||
303 | * Note2: CLOCK_SOURCE is set via 0=32kHz, 1=16MHz, | ||
304 | * 2=24MHz, 3=33MHz, 4=48MHz, 5=SLOW, 6=FAST, 7=PLL. | ||
305 | * SLOW = 24MHz / (DIV_SLOW + 1), DIV = Bits 16-19 | ||
306 | * FAST = PLL / (DIV_FAST + 1), DIV = Bits 20-23 */ | ||
307 | case CPUFREQ_SLEEP: | ||
308 | cpu_frequency = CPUFREQ_SLEEP; | ||
309 | PLL_CONTROL |= 0x0c000000; | ||
310 | scale_suspend_core(true); | ||
311 | CLOCK_SOURCE = 0x20000000; /* source #1, #2, #3, #4: 32kHz (#2 active) */ | ||
312 | scale_suspend_core(false); | ||
313 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | ||
314 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ | ||
315 | break; | ||
316 | |||
317 | case CPUFREQ_MAX: | ||
318 | cpu_frequency = CPUFREQ_MAX; | ||
319 | DEV_INIT2 |= INIT_PLL; /* enable PLL power */ | ||
320 | PLL_CONTROL |= 0x88000000; /* enable PLL */ | ||
321 | scale_suspend_core(true); | ||
322 | CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */ | ||
323 | DEV_TIMING1 = 0x00000303; | ||
324 | scale_suspend_core(false); | ||
325 | #if defined(IPOD_MINI2G) | ||
326 | MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */ | ||
327 | #elif defined(IPOD_NANO) | ||
328 | IDE0_CFG |= 0x10000000; /* set ">65MHz" bit */ | ||
329 | #endif | ||
330 | #if CONFIG_CPU == PP5020 | ||
331 | PLL_CONTROL = 0x8a020a03; /* 80 MHz = 10/3 * 24MHz */ | ||
332 | PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ | ||
333 | PLL_CONTROL = 0x8a020a03; /* repeat setup */ | ||
334 | udelay(500); /* wait for relock */ | ||
335 | #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) | ||
336 | PLL_CONTROL = 0x8a121403; /* 80 MHz = (20/3 * 24MHz) / 2 */ | ||
337 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ | ||
338 | #endif | ||
339 | scale_suspend_core(true); | ||
340 | DEV_TIMING1 = 0x00000808; | ||
341 | CLOCK_SOURCE = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */ | ||
342 | scale_suspend_core(false); | ||
343 | break; | ||
344 | #if 0 /******** CPUFREQ_NORMAL = 24MHz without PLL ********/ | ||
345 | case CPUFREQ_NORMAL: | ||
346 | cpu_frequency = CPUFREQ_NORMAL; | ||
347 | PLL_CONTROL |= 0x08000000; | ||
348 | scale_suspend_core(true); | ||
349 | CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */ | ||
350 | DEV_TIMING1 = 0x00000303; | ||
351 | #if defined(IPOD_MINI2G) | ||
352 | MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ | ||
353 | #elif defined(IPOD_NANO) | ||
354 | IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */ | ||
355 | #endif | ||
356 | scale_suspend_core(false); | ||
357 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | ||
358 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ | ||
359 | break; | ||
360 | #else /******** CPUFREQ_NORMAL = 30MHz with PLL ********/ | ||
361 | case CPUFREQ_NORMAL: | ||
362 | cpu_frequency = CPUFREQ_NORMAL; | ||
363 | DEV_INIT2 |= INIT_PLL; /* enable PLL power */ | ||
364 | PLL_CONTROL |= 0x88000000; /* enable PLL */ | ||
365 | scale_suspend_core(true); | ||
366 | CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */ | ||
367 | DEV_TIMING1 = 0x00000303; | ||
368 | scale_suspend_core(false); | ||
369 | #if defined(IPOD_MINI2G) | ||
370 | MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ | ||
371 | #elif defined(IPOD_NANO) | ||
372 | IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */ | ||
373 | #endif | ||
374 | #if CONFIG_CPU == PP5020 | ||
375 | PLL_CONTROL = 0x8a020504; /* 30 MHz = 5/4 * 24MHz */ | ||
376 | udelay(500); /* wait for relock */ | ||
377 | #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) | ||
378 | PLL_CONTROL = 0x8a220501; /* 30 MHz = (5/1 * 24MHz) / 4 */ | ||
379 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ | ||
380 | #endif | ||
381 | scale_suspend_core(true); | ||
382 | DEV_TIMING1 = 0x00000303; | ||
383 | CLOCK_SOURCE = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */ | ||
384 | scale_suspend_core(false); | ||
385 | break; | ||
386 | #endif /******** CPUFREQ_NORMAL end ********/ | ||
387 | default: | ||
388 | cpu_frequency = CPUFREQ_DEFAULT; | ||
389 | PLL_CONTROL |= 0x08000000; | ||
390 | scale_suspend_core(true); | ||
391 | CLOCK_SOURCE = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */ | ||
392 | DEV_TIMING1 = 0x00000303; | ||
393 | #if defined(IPOD_MINI2G) | ||
394 | MLCD_SCLK_DIV = 0x00000000; /* Mono LCD bridge serial clock divider */ | ||
395 | #elif defined(IPOD_NANO) | ||
396 | IDE0_CFG &= ~0x10000000; /* clear ">65MHz" bit */ | ||
397 | #endif | ||
398 | scale_suspend_core(false); | ||
399 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | ||
400 | DEV_INIT2 &= ~INIT_PLL; /* disable PLL power */ | ||
401 | break; | ||
402 | } | ||
403 | |||
404 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | ||
405 | corelock_unlock(&cpufreq_cl); | ||
406 | #endif | ||
407 | } | ||
408 | #endif /* !BOOTLOADER || (SANSA_E200 || SANSA_C200 || PHILIPS_SA9200) */ | ||
409 | |||
410 | #ifndef BOOTLOADER | ||
411 | void system_init(void) | ||
412 | { | ||
413 | if (CURRENT_CORE == CPU) | ||
414 | { | ||
415 | #if defined (IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_COLOR) | ||
416 | /* set minimum startup configuration */ | ||
417 | DEV_EN = 0xc2000124; | ||
418 | DEV_EN2 = 0x00002000; | ||
419 | CACHE_PRIORITY = 0x0000003f; | ||
420 | GPO32_VAL = 0x20000000; | ||
421 | DEV_INIT1 = 0xdc000000; | ||
422 | DEV_INIT2 = 0x40000000; | ||
423 | |||
424 | /* reset all allowed devices */ | ||
425 | DEV_RS = 0x3dfffef8; | ||
426 | DEV_RS2 = 0xffffdfff; | ||
427 | DEV_RS = 0x00000000; | ||
428 | DEV_RS2 = 0x00000000; | ||
429 | #elif defined (IPOD_VIDEO) | ||
430 | /* set minimum startup configuration */ | ||
431 | DEV_EN = 0xc2000124; | ||
432 | DEV_EN2 = 0x00000000; | ||
433 | CACHE_PRIORITY = 0x0000003f; | ||
434 | GPO32_VAL &= 0x00004000; | ||
435 | DEV_INIT1 = 0x00000000; | ||
436 | DEV_INIT2 = 0x40000000; | ||
437 | |||
438 | /* reset all allowed devices */ | ||
439 | DEV_RS = 0x3dfffef8; | ||
440 | DEV_RS2 = 0xffffffff; | ||
441 | DEV_RS = 0x00000000; | ||
442 | DEV_RS2 = 0x00000000; | ||
443 | #elif defined (IPOD_NANO) | ||
444 | /* set minimum startup configuration */ | ||
445 | DEV_EN = 0xc2000124; | ||
446 | DEV_EN2 = 0x00002000; | ||
447 | CACHE_PRIORITY = 0x0000003f; | ||
448 | GPO32_VAL = 0x50000000; | ||
449 | DEV_INIT1 = 0xa8000000; | ||
450 | DEV_INIT2 = 0x40000000; | ||
451 | |||
452 | /* reset all allowed devices */ | ||
453 | DEV_RS = 0x3ffffef8; | ||
454 | DEV_RS2 = 0xffffdfff; | ||
455 | DEV_RS = 0x00000000; | ||
456 | DEV_RS2 = 0x00000000; | ||
457 | #elif defined(SANSA_C200) || defined (SANSA_E200) | ||
458 | /* set minimum startup configuration */ | ||
459 | DEV_EN = 0xc4000124; | ||
460 | DEV_EN2 = 0x00000000; | ||
461 | CACHE_PRIORITY = 0x0000003f; | ||
462 | GPO32_VAL = 0x10000000; | ||
463 | DEV_INIT1 = 0x54000000; | ||
464 | DEV_INIT2 = 0x40000000; | ||
465 | |||
466 | /* reset all allowed devices */ | ||
467 | DEV_RS = 0x3bfffef8; | ||
468 | DEV_RS2 = 0xffffffff; | ||
469 | DEV_RS = 0x00000000; | ||
470 | DEV_RS2 = 0x00000000; | ||
471 | #elif defined(PHILIPS_SA9200) | ||
472 | /* reset all allowed devices */ | ||
473 | DEV_RS = 0x3ffffef8; | ||
474 | DEV_RS2 = 0xffffffff; | ||
475 | DEV_RS = 0x00000000; | ||
476 | DEV_RS2 = 0x00000000; | ||
477 | #elif defined(IPOD_4G) | ||
478 | /* set minimum startup configuration */ | ||
479 | DEV_EN = 0xc2020124; | ||
480 | DEV_EN2 = 0x00000000; | ||
481 | CACHE_PRIORITY = 0x0000003f; | ||
482 | GPO32_VAL = 0x02000000; | ||
483 | DEV_INIT1 = 0x00000000; | ||
484 | DEV_INIT2 = 0x40000000; | ||
485 | |||
486 | /* reset all allowed devices */ | ||
487 | DEV_RS = 0x3dfdfef8; | ||
488 | DEV_RS2 = 0xffffffff; | ||
489 | DEV_RS = 0x00000000; | ||
490 | DEV_RS2 = 0x00000000; | ||
491 | #elif defined (IPOD_MINI) | ||
492 | /* to be done */ | ||
493 | #elif defined (IPOD_MINI2G) | ||
494 | /* to be done */ | ||
495 | #elif defined (MROBE_100) | ||
496 | /* to be done */ | ||
497 | #elif defined (TATUNG_TPJ1022) | ||
498 | /* to be done */ | ||
499 | #elif defined(PBELL_VIBE500) | ||
500 | /* reset all allowed devices */ | ||
501 | DEV_RS = 0x3ffffef8; | ||
502 | DEV_RS2 = 0xffffffff; | ||
503 | DEV_RS = 0x00000000; | ||
504 | DEV_RS2 = 0x00000000; | ||
505 | #endif | ||
506 | |||
507 | #if !defined(SANSA_E200) && !defined(SANSA_C200) && !defined(PHILIPS_SA9200) | ||
508 | /* Remap the flash ROM on CPU, keep hidden from COP: | ||
509 | * 0x00000000-0x3fffffff = 0x20000000-0x23ffffff */ | ||
510 | MMAP1_LOGICAL = 0x20003c00; | ||
511 | MMAP1_PHYSICAL = 0x00003084 | | ||
512 | MMAP_PHYS_READ_MASK | MMAP_PHYS_WRITE_MASK | | ||
513 | MMAP_PHYS_DATA_MASK | MMAP_PHYS_CODE_MASK; | ||
514 | #endif | ||
515 | |||
516 | disable_all_interrupts(); | ||
517 | |||
518 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | ||
519 | #if NUM_CORES > 1 | ||
520 | corelock_init(&cpufreq_cl); | ||
521 | cpu_boost_init(); | ||
522 | #endif | ||
523 | #else | ||
524 | pp_set_cpu_frequency(CPUFREQ_MAX); | ||
525 | #endif | ||
526 | |||
527 | #if defined(IPOD_VIDEO) | ||
528 | /* crt0-pp.S wrote the ram size to the last byte of the first 32MB | ||
529 | ram bank. See the comment there for how we determine it. */ | ||
530 | volatile unsigned char *end32 = (volatile unsigned char *)0x01ffffff; | ||
531 | probed_ramsize = *end32; | ||
532 | #endif | ||
533 | } | ||
534 | |||
535 | init_cache(); | ||
536 | } | ||
537 | |||
538 | #else /* BOOTLOADER */ | ||
539 | |||
540 | void system_init(void) | ||
541 | { | ||
542 | /* Only the CPU gets here in the bootloader */ | ||
543 | #ifdef HAVE_BOOTLOADER_USB_MODE | ||
544 | disable_all_interrupts(); | ||
545 | init_cache(); | ||
546 | /* Use the local vector map */ | ||
547 | CACHE_CTL |= CACHE_CTL_VECT_REMAP; | ||
548 | #endif /* HAVE_BOOTLOADER_USB_MODE */ | ||
549 | |||
550 | #if defined(SANSA_C200) || defined(SANSA_E200) || defined(PHILIPS_SA9200) | ||
551 | pp_set_cpu_frequency(CPUFREQ_MAX); | ||
552 | #endif | ||
553 | /* Else the frequency should get changed upon USB connect - | ||
554 | * decide per-target */ | ||
555 | } | ||
556 | |||
557 | #ifdef HAVE_BOOTLOADER_USB_MODE | ||
558 | void system_prepare_fw_start(void) | ||
559 | { | ||
560 | disable_interrupt(IRQ_FIQ_STATUS); | ||
561 | tick_stop(); | ||
562 | disable_all_interrupts(); | ||
563 | /* Some OF's disable this themselves, others do not and will hang. */ | ||
564 | CACHE_CTL &= ~CACHE_CTL_VECT_REMAP; | ||
565 | } | ||
566 | #endif /* HAVE_BOOTLOADER_USB_MODE */ | ||
567 | #endif /* !BOOTLOADER */ | ||
568 | |||
569 | void ICODE_ATTR system_reboot(void) | ||
570 | { | ||
571 | disable_interrupt(IRQ_FIQ_STATUS); | ||
572 | CPU_INT_DIS = -1; | ||
573 | COP_INT_DIS = -1; | ||
574 | |||
575 | /* Reboot */ | ||
576 | #if defined(SANSA_E200) || defined(SANSA_C200) || defined(PHILIPS_SA9200) | ||
577 | CACHE_CTL &= ~CACHE_CTL_VECT_REMAP; | ||
578 | |||
579 | /* Magic used by the c200 OF: 0x23066000 | ||
580 | Magic used by the c200 BL: 0x23066b7b | ||
581 | In both cases, the OF executes these 2 commands from iram. */ | ||
582 | STRAP_OPT_A = 0x23066b7b; | ||
583 | DEV_RS = DEV_SYSTEM; | ||
584 | #else | ||
585 | DEV_RS |= DEV_SYSTEM; | ||
586 | #endif | ||
587 | /* wait until reboot kicks in */ | ||
588 | while (1); | ||
589 | } | ||
590 | |||
591 | void system_exception_wait(void) | ||
592 | { | ||
593 | /* FIXME: we just need the right buttons */ | ||
594 | CPU_INT_DIS = -1; | ||
595 | COP_INT_DIS = -1; | ||
596 | |||
597 | /* Halt */ | ||
598 | PROC_CTL(CURRENT_CORE) = 0x40000000; | ||
599 | while (1); | ||
600 | } | ||
601 | |||
602 | int system_memory_guard(int newmode) | ||
603 | { | ||
604 | (void)newmode; | ||
605 | return 0; | ||
606 | } | ||
607 | |||