Revise the PCM callback system after adding multichannel audio.

Additional status callback is added to pcm_play/rec_data instead of
using a special function to set it. Status includes DMA error
reporting to the status callback. Playback and recording callback
become more alike except playback uses "const void **addr" (because
the data should not be altered) and recording  uses "void **addr".
"const" is put in place throughout where appropriate.

Most changes are fairly trivial. One that should be checked in
particular because it isn't so much is telechips, if anyone cares to
bother. PP5002 is not so trivial either but that tested as working.

Change-Id: I4928d69b3b3be7fb93e259f81635232df9bd1df2
Reviewed-on: http://gerrit.rockbox.org/166
Reviewed-by: Michael Sevakis <jethead71@rockbox.org>
Tested-by: Michael Sevakis <jethead71@rockbox.org>

1 files changed, 314 insertions, 313 deletions

diff --git a/firmware/target/arm/pp/pcm-pp.c b/firmware/target/arm/pp/pcm-pp.c
index 1b38994f7b..99d46a6096 100644
--- a/firmware/target/arm/pp/pcm-pp.c
+++ b/firmware/target/arm/pp/pcm-pp.c
@@ -30,26 +30,6 @@
 
 /** DMA **/
 
-#ifdef CPU_PP502x
-/* 16-bit, L-R packed into 32 bits with left in the least significant halfword */
-#define SAMPLE_SIZE   16
-/* DMA Requests from IIS, Memory to peripheral, single transfer,
-   wait for DMA request, interrupt on complete */
-#define DMA_PLAY_CONFIG ((DMA_REQ_IIS << DMA_CMD_REQ_ID_POS) | \
-                          DMA_CMD_RAM_TO_PER | DMA_CMD_SINGLE | \
-                          DMA_CMD_WAIT_REQ | DMA_CMD_INTR)
-/* DMA status cannot be viewed from outside code in control because that can
- * clear the interrupt from outside the handler and prevent the handler from
- * from being called. Split up transfers to a reasonable size that is good as
- * a timer, obtaining a keyclick position and peaking yet still keeps the
- * FIQ count low.
- */
-#define MAX_DMA_CHUNK_SIZE (pcm_curr_sampr >> 6) /* ~1/256 seconds */
-#else
-/* 32-bit, one left 32-bit sample followed by one right 32-bit sample */
-#define SAMPLE_SIZE   32
-#endif
-
 struct dma_data
 {
 /* NOTE: The order of size and p is important if you use assembler
@@ -57,6 +37,8 @@ struct dma_data
     union
     {
         unsigned long addr;
+        const void *p_r;
+        void *p_w;
         uint32_t *p16;  /* For packed 16-16 stereo pairs */
         uint16_t *p32;  /* For individual samples converted to 32-bit */
     };
@@ -113,56 +95,208 @@ void pcm_dma_apply_settings(void)
 }
 
 #if defined(CPU_PP502x)
-/* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
-void ICODE_ATTR __attribute__((interrupt("FIQ"))) fiq_playback(void)
+/* 16-bit, L-R packed into 32 bits with left in the least significant halfword */
+#define SAMPLE_SIZE   16
+/* DMA Requests from IIS, Memory to peripheral, single transfer,
+   wait for DMA request, interrupt on complete */
+#define DMA_PLAY_CONFIG ((DMA_REQ_IIS << DMA_CMD_REQ_ID_POS) | \
+                          DMA_CMD_RAM_TO_PER | DMA_CMD_SINGLE | \
+                          DMA_CMD_WAIT_REQ | DMA_CMD_INTR)
+/* DMA status cannot be viewed from outside code in control because that can
+ * clear the interrupt from outside the handler and prevent the handler from
+ * from being called. Split up transfers to a reasonable size that is good as
+ * a timer and peaking yet still keeps the FIQ count low.
+ */
+#define MAX_DMA_CHUNK_SIZE (pcm_curr_sampr >> 6) /* ~1/256 seconds */
+
+static inline void dma_tx_init(void)
+{
+    /* Enable DMA controller */
+    DMA_MASTER_CONTROL |= DMA_MASTER_CONTROL_EN;
+    /* FIQ priority for DMA */
+    CPU_INT_PRIORITY |= DMA_MASK;
+    /* Enable request?? Not setting or clearing everything doesn't seem to
+     * prevent it operating. Perhaps important for reliability (how requests
+     * are handled). */
+    DMA_REQ_STATUS |= 1ul << DMA_REQ_IIS;
+    DMA0_STATUS;
+}
+
+static inline void dma_tx_setup(void)
+{
+    /* Setup DMA controller */
+    DMA0_PER_ADDR = (unsigned long)&IISFIFO_WR;
+    DMA0_FLAGS = DMA_FLAGS_UNK26;
+    DMA0_INCR = DMA_INCR_RANGE_FIXED | DMA_INCR_WIDTH_32BIT;
+}
+
+static inline unsigned long dma_tx_buf_prepare(const void *addr)
+{
+    unsigned long a = (unsigned long)addr;
+
+    if (a < UNCACHED_BASE_ADDR) {
+        /* VA in DRAM - writeback all data and get PA */
+        a = UNCACHED_ADDR(a);
+        commit_dcache();
+    }
+
+    return a;
+}
+
+static inline void dma_tx_start(bool begin)
+{
+    size_t size = MAX_DMA_CHUNK_SIZE;
+
+    /* Not at least MAX_DMA_CHUNK_SIZE left or there would be less
+     * than a FIFO's worth of data after this transfer? */
+    if (size + 16*4 > dma_play_data.size)
+        size = dma_play_data.size;
+
+    /* Set the new DMA values and activate channel */
+    DMA0_RAM_ADDR = dma_play_data.addr;
+    DMA0_CMD = DMA_PLAY_CONFIG | (size - 4) | DMA_CMD_START;
+
+    (void)begin;
+}
+
+static void dma_tx_stop(void)
+{
+    unsigned long status = DMA0_STATUS; /* Snapshot- resume from this point */
+    unsigned long cmd = DMA0_CMD;
+    size_t size = 0;
+
+    /* Stop transfer */
+    DMA0_CMD = cmd & ~(DMA_CMD_START | DMA_CMD_INTR);
+
+    /* Wait for not busy + clear int */
+    while (DMA0_STATUS & (DMA_STATUS_BUSY | DMA_STATUS_INTR));
+
+    if (status & DMA_STATUS_BUSY) {
+        /* Transfer was interrupted - leave what's left */
+        size = (cmd & 0xfffc) - (status & 0xfffc);
+    }
+    else if (status & DMA_STATUS_INTR) {
+        /* Transfer was finished - DMA0_STATUS will have been reloaded
+         * automatically with size in DMA0_CMD. Setup to restart on next
+         * segment. */
+        size = (cmd & 0xfffc) + 4;
+    }
+    /* else not an active state - size = 0 */
+
+    dma_play_data.addr += size;
+    dma_play_data.size -= size;
+
+    if (dma_play_data.size == 0)
+        dma_play_data.addr = 0; /* Entire buffer has completed. */
+}
+
+static inline void dma_tx_lock(void)
+{
+    CPU_INT_DIS = DMA_MASK;
+}
+
+static inline void dma_tx_unlock(void)
 {
-    bool new_buffer = false;
-    register size_t size;
+    CPU_INT_EN = DMA_MASK;
+}
 
+/* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
+void fiq_playback(void) ICODE_ATTR __attribute__((interrupt("FIQ")));
+void fiq_playback(void)
+{
     DMA0_STATUS; /* Clear any pending interrupt */
 
-    size = (DMA0_CMD & 0xffff) + 4; /* Get size of trasfer that caused this
-                                       interrupt */
+    size_t size = (DMA0_CMD & 0xffff) + 4; /* Get size of trasfer that caused
+                                              this interrupt */
     dma_play_data.addr += size;
     dma_play_data.size -= size;
 
-    while (1)
-    {
-        if (dma_play_data.size > 0) {
-            size = MAX_DMA_CHUNK_SIZE;
-            /* Not at least MAX_DMA_CHUNK_SIZE left or there would be less
-             * than a FIFO's worth of data after this transfer? */
-            if (size + 16*4 > dma_play_data.size)
-                size = dma_play_data.size;
-
-            /* Set the new DMA values and activate channel */
-            DMA0_RAM_ADDR = dma_play_data.addr;
-            DMA0_CMD = DMA_PLAY_CONFIG | (size - 4) | DMA_CMD_START;
-
-            if (new_buffer)
-                pcm_play_dma_started_callback();
-            return;
-        }
+    if (LIKELY(dma_play_data.size != 0)) {
+        /* Begin next segment */
+        dma_tx_start(false);
+    }
+    else if (pcm_play_dma_complete_callback(PCM_DMAST_OK, &dma_play_data.p_r,
+                                            &dma_play_data.size)) {
+        dma_play_data.addr = dma_tx_buf_prepare(dma_play_data.p_r);
+        dma_tx_start(false);
+        pcm_play_dma_status_callback(PCM_DMAST_STARTED);
+    }
+}
 
-        new_buffer = true;
+#else /* !defined (CPU_PP502x) */
 
-        /* Buffer empty.  Try to get more. */
-        pcm_play_get_more_callback((void **)&dma_play_data.addr,
-                                   &dma_play_data.size);
+/* 32-bit, one left 32-bit sample followed by one right 32-bit sample */
+#define SAMPLE_SIZE   32
 
-        if (dma_play_data.size == 0) {
-            /* No more data */
-            return;
-        }
+static void dma_tx_init(void)
+{
+    /* Set up banked registers for FIQ mode */
 
-        if (dma_play_data.addr < UNCACHED_BASE_ADDR) {
-            /* Flush any pending cache writes */
-            dma_play_data.addr = UNCACHED_ADDR(dma_play_data.addr);
-            commit_dcache();
-        }
+    /* Use non-banked registers for scratch. */
+    register volatile void *iiscfg asm("r0") = &IISCONFIG;
+    register volatile void *dmapd asm("r1") = &dma_play_data;
+
+    asm volatile (
+        "mrs    r2, cpsr            \n" /* Save mode and interrupt status */
+        "msr    cpsr_c, #0xd1       \n" /* Switch to FIQ mode */
+        "mov    r8, #0              \n"
+        "mov    r9, #0              \n"
+        "mov    r10, %[iiscfg]      \n"
+        "mov    r11, %[dmapd]       \n"
+        "msr    cpsr_c, r2          \n"
+        :
+        : [iiscfg]"r"(iiscfg), [dmapd]"r"(dmapd)
+        : "r2");
+
+    /* FIQ priority for I2S */
+    CPU_INT_PRIORITY |= IIS_MASK;
+    CPU_INT_EN = IIS_MASK;
+}
+
+static inline void dma_tx_setup(void)
+{
+    /* Nothing to do */
+}
+
+static inline unsigned long dma_tx_buf_prepare(const void *addr)
+{
+    return (unsigned long)addr;
+}
+
+static inline void dma_tx_start(bool begin)
+{
+    if (begin) {
+        IISCONFIG &= ~IIS_TXFIFOEN; /* Stop transmitting */
     }
+
+    /* Fill the FIFO or start when data is used up */
+    while (IIS_TX_FREE_COUNT >= 2 && dma_play_data.size != 0) {
+        IISFIFO_WRH = *dma_play_data.p32++;
+        IISFIFO_WRH = *dma_play_data.p32++;
+        dma_play_data.size -= 4;
+    }
+
+    if (begin) {
+        IISCONFIG |= IIS_TXFIFOEN; /* Start transmitting */
+    }
+}
+
+static inline void dma_tx_stop(void)
+{
+    /* Disable TX interrupt */
+    IIS_IRQTX_REG &= ~IIS_IRQTX;
+}
+
+static inline void dma_tx_lock(void)
+{
+    IIS_IRQTX_REG &= ~IIS_IRQTX;
+}
+
+static inline void dma_tx_unlock(void)
+{
+    IIS_IRQTX_REG |= IIS_IRQTX;
 }
-#else
+
 /* ASM optimised FIQ handler. Checks for the minimum allowed loop cycles by
  * evalutation of free IISFIFO-slots against available source buffer words.
  * Through this it is possible to move the check for IIS_TX_FREE_COUNT outside
@@ -173,150 +307,123 @@ void ICODE_ATTR __attribute__((interrupt("FIQ"))) fiq_playback(void)
  * ASM implementation (not used anymore): GCC fails to make use of the fact
  * that FIQ mode has registers r8-r14 banked, and so does not need to be saved.
  * This routine uses only these registers, and so will never touch the stack
- * unless it actually needs to do so when calling pcm_callback_for_more.
+ * unless it actually needs to do so when calling pcm_play_dma_complete_callback.
  * C version is still included below for reference and testing.
  */
 #if 1
 void fiq_playback(void) ICODE_ATTR __attribute__((naked));
 void fiq_playback(void)
 {
-    /* r10 contains IISCONFIG address (set in crt0.S to minimise code in actual
-     * FIQ handler. r11 contains address of p (also set in crt0.S). Most other
-     * addresses we need are generated by using offsets with these two.
-     * r10 + 0x40 is IISFIFO_WR, and r10 + 0x0c is IISFIFO_CFG.
-     * r8 and r9 contains local copies of p and size respectively.
-     * r0-r3 and r12 is a working register.
+    /* r8 and r9 contains local copies of p and size respectively.
+     * r10 contains IISCONFIG address (set during PCM init to minimize code in
+     * FIQ handler.Most other addresses we need are generated by using offsets
+     * from this.
+     * r10 + 0x40 is IISFIFO_WR, and r10 + 0x1c is IISFIFO_CFG.
+     * r11 contains address of dma_play_data
+     * r12 and r14 are working registers.
+     *
+     * Divided into two blocks: one where no external calls are needed and
+     * one where external callbacks are made
      */
     asm volatile (
-        "stmfd   sp!, { r0-r4, lr }  \n" /* stack scratch regs and lr */
-
-        "mov     r4, #0              \n" /* Was the callback called? */
-#if CONFIG_CPU == PP5002
-        "ldr     r12, =0xcf001040    \n" /* Some magic from iPodLinux */
-        "ldr     r12, [r12]          \n"
-#endif
-        "ldmia   r11, { r8-r9 }      \n" /* r8 = p, r9 = size */
-        "cmp     r9, #0              \n" /* is size 0? */
-        "beq     .more_data          \n" /* if so, ask pcmbuf for more data */
-
-#if SAMPLE_SIZE == 16
-    ".check_fifo:                    \n"   
-        "ldr     r0, [r10, %[cfg]]   \n" /* read IISFIFO_CFG to check FIFO status */
-        "and     r0, r0, %[mask]     \n" /* r0 = IIS_TX_FREE_COUNT << 16 (PP502x) */
-
-        "mov     r1, r0, lsr #16     \n" /* number of free FIFO slots */
-        "cmp     r1, r9, lsr #2      \n" /* number of words from source */
-        "movgt   r1, r9, lsr #2      \n" /* r1 = amount of allowed loops */
-        "sub     r9, r9, r1, lsl #2  \n" /* r1 words will be written in following loop */
-
-        "subs    r1, r1, #2          \n"
-    ".fifo_loop_2:                   \n"
-        "ldmgeia r8!, {r2, r12}      \n" /* load four samples */
-        "strge   r2 , [r10, %[wr]]   \n" /* write sample 0-1 to IISFIFO_WR */
-        "strge   r12, [r10, %[wr]]   \n" /* write sample 2-3 to IISFIFO_WR */
-        "subges  r1, r1, #2          \n" /* one more loop? */
-        "bge     .fifo_loop_2        \n" /* yes, continue */
-
-        "tst     r1, #1              \n" /* two samples (one word) left? */
-        "ldrne   r12, [r8], #4       \n" /* load two samples */
-        "strne   r12, [r10, %[wr]]   \n" /* write sample 0-1 to IISFIFO_WR */
-#elif SAMPLE_SIZE == 32
-    ".check_fifo:                    \n"
-        "ldr     r0, [r10, %[cfg]]   \n" /* read IISFIFO_CFG to check FIFO status */
-        "and     r0, r0, %[mask]     \n" /* r0 = IIS_TX_FREE_COUNT << 23 (PP5002) */
-
-        "movs    r1, r0, lsr #24     \n" /* number of free pairs of FIFO slots */
-        "beq     .fifo_fill_complete \n" /* no complete pair? -> exit */
-        "cmp     r1, r9, lsr #2      \n" /* number of words from source */
-        "movgt   r1, r9, lsr #2      \n" /* r1 = amount of allowed loops */
-        "sub     r9, r9, r1, lsl #2  \n" /* r1 words will be written in following loop */
-
-    ".fifo_loop:                     \n"
-        "ldr     r12, [r8], #4       \n" /* load two samples */
-        "mov     r2 , r12, lsl #16   \n" /* put left sample at the top bits */
-        "str     r2 , [r10, %[wr]]   \n" /* write top sample to IISFIFO_WR */
-        "str     r12, [r10, %[wr]]   \n" /* write low sample to IISFIFO_WR*/
-        "subs    r1, r1, #1          \n" /* one more loop? */
-        "bgt     .fifo_loop          \n" /* yes, continue */
-
-    ".fifo_fill_complete:            \n"
-#endif
-        "cmp     r4, #0              \n" /* If fill came after get_more... */
-        "beq     .still_old_buffer   \n"
-        "mov     r4, #0              \n"
-        "ldr     r2, =pcm_play_dma_started \n"
-        "ldrne   r2, [r2]            \n"
-        "cmp     r2, #0              \n"
-        "movne   lr, pc              \n"
-        "bxne    r2                  \n"
-
-    ".still_old_buffer:              \n"
-        "cmp     r9, #0              \n" /* either FIFO is full or source buffer is empty */
-        "bgt     .exit               \n" /* if source buffer is not empty, FIFO must be full */
-
-    ".more_data:                     \n"
-        "mov     r4, #1              \n" /* Remember we did this */
-        "ldr     r2, =pcm_play_get_more_callback \n"
-        "mov     r0, r11             \n" /* r0 = &p */
-        "add     r1, r11, #4         \n" /* r1 = &size */
-        "mov     lr, pc              \n" /* call pcm_play_get_more_callback */
-        "bx      r2                  \n"
-        "ldmia   r11, { r8-r9 }      \n" /* load new p and size */
-        "cmp     r9, #0              \n"
-        "bne     .check_fifo         \n" /* size != 0? refill */
-
-    ".exit:                          \n" /* (r9=0 if stopping, look above) */
-        "stmia   r11, { r8-r9 }      \n" /* save p and size */
-        "ldmfd   sp!, { r0-r4, lr }  \n"
-        "subs    pc, lr, #4          \n" /* FIQ specific return sequence */
-        ".ltorg                      \n"
+    /* No external calls */
+        "sub     lr, lr, #4           \n" /* Prepare return address */
+        "stmfd   sp!, { lr }          \n" /* stack lr so we can use it */
+        "ldr     r12, =0xcf001040     \n" /* Some magic from iPodLinux ... */
+        "ldr     r12, [r12]           \n" /* ... actually a DMA INT ack? */
+        "ldmia   r11, { r8-r9 }       \n" /* r8 = p, r9 = size */
+        "cmp     r9, #0               \n" /* is size 0? */
+        "beq     1f                   \n" /* if so, ask PCM for more data */
+
+        "ldr     r14, [r10, #0x1c]    \n" /* read IISFIFO_CFG to check FIFO status */
+        "and     r14, r14, #(0xe<<23) \n" /* r14 = (IIS_TX_FREE_COUNT & ~1) << 23 */
+        "cmp     r9, r14, lsr #22     \n" /* number of words from source */
+        "movlo   r14, r9, lsl #22     \n" /* r14 = amount of allowed loops */
+        "sub     r9, r9, r14, lsr #22 \n" /* r14 words will be written in loop */
+    "0:                               \n"
+        "ldr     r12, [r8], #4        \n" /* load left-right pair */
+        "subs    r14, r14, #(0x2<<23) \n" /* one more loop? ... */
+        "strh    r12, [r10, #0x40]    \n" /* left sample to IISFIFO_WR */
+        "mov     r12, r12, lsr #16    \n" /* put right sample in bottom 16 bits */
+        "strh    r12, [r10, #0x40]    \n" /* right sample to IISFIFO_WR */
+        "bhi     0b                   \n" /* ... yes, continue */
+
+        "cmp     r9, #0               \n" /* either FIFO full or size empty? */
+        "stmneia r11, { r8-r9 }       \n" /* save p and size, if not empty */
+        "ldmnefd sp!, { pc }^         \n" /* RFE if not empty */
+
+    /* Making external calls */
+    "1:                               \n"
+        "stmfd   sp!, { r0-r3 }       \n" /* Must save volatiles */
+    "2:                               \n"
+        "mov     r0, %0               \n" /* r0 = status */
+        "mov     r1, r11              \n" /* r1 = &dma_play_data.p_r */
+        "add     r2, r11, #4          \n" /* r2 = &dma_play_data.size */
+        "ldr     r3, =pcm_play_dma_complete_callback \n"
+        "mov     lr, pc               \n" /* long call (not in same section) */
+        "bx      r3                   \n"
+        "cmp     r0, #0               \n" /* more data? */
+        "ldmeqfd sp!, { r0-r3, pc }^  \n" /* no? -> exit */
+
+        "ldr     r14, [r10, #0x1c]    \n" /* read IISFIFO_CFG to check FIFO status */
+        "ands    r14, r14, #(0xe<<23) \n" /* r14 = (IIS_TX_FREE_COUNT & ~1) << 23 */
+        "bne     4f                   \n"
+    "3:                               \n" /* inform of started status if registered */
+        "ldr     r1, =pcm_play_status_callback \n"
+        "ldr     r1, [r1]             \n"
+        "cmp     r1, #0               \n"
+        "movne   r0, %1               \n"
+        "movne   lr, pc               \n"
+        "bxne    r1                   \n"
+        "ldmfd   sp!, { r0-r3, pc }^  \n" /* exit */
+    "4:                               \n"
+        "ldmia   r11, { r8-r9 }       \n" /* load new p and size */
+        "cmp     r9, r14, lsr #22     \n" /* number of words from source */
+        "movlo   r14, r9, lsl #22     \n" /* r14 = amount of allowed loops */
+        "sub     r9, r9, r14, lsr #22 \n" /* r14 words will be written in loop */
+    "0:                               \n"
+        "ldr     r12, [r8], #4        \n" /* load left-right pair */
+        "subs    r14, r14, #(0x2<<23) \n" /* one more loop? ... */
+        "strh    r12, [r10, #0x40]    \n" /* left sample to IISFIFO_WR */
+        "mov     r12, r12, lsr #16    \n" /* put right sample in bottom 16 bits */
+        "strh    r12, [r10, #0x40]    \n" /* right sample to IISFIFO_WR */
+        "bhi     0b                   \n" /* ... yes, continue */
+        "stmia   r11, { r8-r9 }       \n" /* save p and size */
+
+        "cmp     r9, #0               \n" /* used up data in FIFO fill? */
+        "bne     3b                   \n" /* no? -> go return */
+        "b       2b                   \n" /* yes -> get even more */
+        ".ltorg                       \n"
         : /* These must only be integers! No regs */
-        : [mask]"i"(IIS_TX_FREE_MASK),
-          [cfg]"i"((int)&IISFIFO_CFG - (int)&IISCONFIG),
-          [wr]"i"((int)&IISFIFO_WR - (int)&IISCONFIG)
-    );
+        : "i"(PCM_DMAST_OK), "i"(PCM_DMAST_STARTED));
 }
+
 #else /* C version for reference */
-void fiq_playback(void) __attribute__((interrupt ("FIQ"))) ICODE_ATTR;
+
 /* NOTE: direct stack use forbidden by GCC stack handling bug for FIQ */
+void fiq_playback(void) ICODE_ATTR __attribute__((interrupt ("FIQ")));
 void fiq_playback(void)
 {
-    bool new_buffer = false;
-
-#if CONFIG_CPU == PP5002
     inl(0xcf001040);
-#endif
 
-    do {
-        while (dma_play_data.size > 0) {
-            if (IIS_TX_FREE_COUNT < 2) {
-                if (new_buffer) {
-                    new_buffer = false;
-                    pcm_play_dma_started_callback();
-                }
-                return;
-            }
-#if SAMPLE_SIZE == 16
-            IISFIFO_WR = *dma_play_data.p16++;
-#elif SAMPLE_SIZE == 32
-            IISFIFO_WR = *dma_play_data.p32++ << 16;
-            IISFIFO_WR = *dma_play_data.p32++ << 16;
-#endif
-            dma_play_data.size -= 4;
-        }
+    if (LIKELY(dma_play_data.size != 0)) {
+        dma_tx_start(false);
 
-        if (new_buffer) {
-            new_buffer = false;
-            pcm_play_dma_started_callback();
+        if (dma_play_data.size != 0) {
+            /* Still more data */
+            return;
         }
+    }
 
-        /* p is empty, get some more data */
-        pcm_play_get_more_callback((void **)&dma_play_data.addr,
-                                   &dma_play_data.size);
-        new_buffer = true;
-    } while (dma_play_data.size);
+    while (pcm_play_dma_complete_callback(PCM_DMAST_OK, &dma_play_data.p_r,
+                                          &dma_play_data.size)) {
+        dma_tx_start(false);
+        pcm_play_dma_status_callback(PCM_DMAST_STARTED);
 
-    /* No more data  */
+        if (dma_play_data.size != 0) {
+            return;
+        }
+    }
 }
 #endif /* ASM / C selection */
 #endif /* CPU_PP502x */
@@ -329,11 +436,7 @@ void pcm_play_lock(void)
     int status = disable_fiq_save();
 
     if (++dma_play_data.locked == 1) {
-#ifdef CPU_PP502x
-        CPU_INT_DIS = DMA_MASK;
-#else
-        IIS_IRQTX_REG &= ~IIS_IRQTX;
-#endif
+        dma_tx_lock();
     }
 
     restore_fiq(status);
@@ -341,89 +444,25 @@ void pcm_play_lock(void)
 
 void pcm_play_unlock(void)
 {
-   int status = disable_fiq_save();
+    int status = disable_fiq_save();
 
     if (--dma_play_data.locked == 0 && dma_play_data.state != 0) {
-#ifdef CPU_PP502x
-        CPU_INT_EN = DMA_MASK;
-#else
-        IIS_IRQTX_REG |= IIS_IRQTX;
-#endif
+        dma_tx_unlock();
     }
 
-   restore_fiq(status);
+    restore_fiq(status);
 }
 
 static void play_start_pcm(void)
 {
     fiq_function = fiq_playback;
-
-#ifdef CPU_PP502x
-    /* Not at least MAX_DMA_CHUNK_SIZE left or there would be less than a
-     * FIFO's worth of data after this transfer? */
-    size_t size = MAX_DMA_CHUNK_SIZE;
-    if (size + 16*4 > dma_play_data.size)
-        size = dma_play_data.size;
-
-    DMA0_RAM_ADDR = dma_play_data.addr;
-    DMA0_CMD = DMA_PLAY_CONFIG | (size - 4) | DMA_CMD_START;
     dma_play_data.state = 1;
-#else
-    IISCONFIG &= ~IIS_TXFIFOEN;  /* Stop transmitting */
-
-    /* Fill the FIFO or start when data is used up */
-    while (1) {
-        if (IIS_TX_FREE_COUNT < 2 || dma_play_data.size == 0) {
-            IISCONFIG |= IIS_TXFIFOEN; /* Start transmitting */
-            dma_play_data.state = 1;
-            return;
-        }
-
-#if SAMPLE_SIZE == 16
-        IISFIFO_WR = *dma_play_data.p16++;
-#elif SAMPLE_SIZE == 32
-        IISFIFO_WR = *dma_play_data.p32++ << 16;
-        IISFIFO_WR = *dma_play_data.p32++ << 16;
-#endif
-        dma_play_data.size -= 4;
-    }
-#endif
+    dma_tx_start(true);
 }
 
 static void play_stop_pcm(void)
 {
-#ifdef CPU_PP502x
-    unsigned long status = DMA0_STATUS; /* Snapshot- resume from this point */
-    unsigned long cmd = DMA0_CMD;
-    size_t size = 0;
-
-    /* Stop transfer */
-    DMA0_CMD = cmd & ~(DMA_CMD_START | DMA_CMD_INTR);
-
-    /* Wait for not busy + clear int */
-    while (DMA0_STATUS & (DMA_STATUS_BUSY | DMA_STATUS_INTR));
-
-    if (status & DMA_STATUS_BUSY) {
-        /* Transfer was interrupted - leave what's left */
-        size = (cmd & 0xfffc) - (status & 0xfffc);
-    }
-    else if (status & DMA_STATUS_INTR) {
-        /* Transfer was finished - DMA0_STATUS will have been reloaded
-         * automatically with size in DMA0_CMD. Setup to restart on next
-         * segment. */
-        size = (cmd & 0xfffc) + 4;
-    }
-    /* else not an active state - size = 0 */
-
-    dma_play_data.addr += size;
-    dma_play_data.size -= size;
-
-    if (dma_play_data.size == 0)
-        dma_play_data.addr = 0; /* Entire buffer has completed. */
-#else
-    /* Disable TX interrupt */
-    IIS_IRQTX_REG &= ~IIS_IRQTX;
-#endif
+    dma_tx_stop();
 
     /* Wait for FIFO to empty */
     while (!IIS_TX_IS_EMPTY);
@@ -433,30 +472,17 @@ static void play_stop_pcm(void)
 
 void pcm_play_dma_start(const void *addr, size_t size)
 {
+    pcm_play_dma_stop();
+
 #if NUM_CORES > 1
     /* This will become more important later - and different ! */
     dma_play_data.core = processor_id(); /* save initiating core */
 #endif
 
-    pcm_play_dma_stop();
-
-#ifdef CPU_PP502x
-    if ((unsigned long)addr < UNCACHED_BASE_ADDR) {
-        /* Flush any pending cache writes */
-        addr = UNCACHED_ADDR(addr);
-        commit_dcache();
-    }
+    dma_tx_setup();
 
-    dma_play_data.addr = (unsigned long)addr;
+    dma_play_data.addr = dma_tx_buf_prepare(addr);
     dma_play_data.size = size;
-    DMA0_PER_ADDR = (unsigned long)&IISFIFO_WR;
-    DMA0_FLAGS = DMA_FLAGS_UNK26;
-    DMA0_INCR = DMA_INCR_RANGE_FIXED | DMA_INCR_WIDTH_32BIT;
-#else
-    dma_play_data.addr = (unsigned long)addr;
-    dma_play_data.size = size;
-#endif
-
     play_start_pcm();
 }
 
@@ -490,39 +516,7 @@ void pcm_play_dma_init(void)
     /* Initialize default register values. */
     audiohw_init();
 
-#ifdef CPU_PP502x
-    /* Enable DMA controller */
-    DMA_MASTER_CONTROL |= DMA_MASTER_CONTROL_EN;
-    /* FIQ priority for DMA */
-    CPU_INT_PRIORITY |= DMA_MASK;
-    /* Enable request?? Not setting or clearing everything doesn't seem to
-     * prevent it operating. Perhaps important for reliability (how requests
-     * are handled). */
-    DMA_REQ_STATUS |= 1ul << DMA_REQ_IIS;
-    DMA0_STATUS;
-#else
-    /* Set up banked registers for FIQ mode */
-
-    /* Use non-banked registers for scratch. */
-    register volatile void *iiscfg asm("r0") = &IISCONFIG;
-    register volatile void *dmapd asm("r1") = &dma_play_data;
-
-    asm volatile (
-        "mrs    r2, cpsr            \n" /* Save mode and interrupt status */
-        "msr    cpsr_c, #0xd1       \n" /* Switch to FIQ mode */
-        "mov    r8, #0              \n"
-        "mov    r9, #0              \n"
-        "mov    r10, %[iiscfg]      \n"
-        "mov    r11, %[dmapd]       \n"
-        "msr    cpsr_c, r2          \n"
-        :
-        : [iiscfg]"r"(iiscfg), [dmapd]"r"(dmapd)
-        : "r2");
-
-    /* FIQ priority for I2S */
-    CPU_INT_PRIORITY |= IIS_MASK;
-    CPU_INT_EN = IIS_MASK;
-#endif
+    dma_tx_init();
 
     IISCONFIG |= IIS_TXFIFOEN;
 }
@@ -649,11 +643,15 @@ void fiq_record(void)
         }
     }
 
-    pcm_rec_more_ready_callback(0, (void *)&dma_rec_data.addr,
-                                &dma_rec_data.size);
+    if (pcm_rec_dma_complete_callback(PCM_DMAST_OK, &dma_rec_data.p_w,
+                                      &dma_rec_data.size))
+    {
+        pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
+    }
 }
 
-#else
+#else /* !(SANSA_C200 || SANSA_E200) */
+
 void fiq_record(void)
 {
     while (dma_rec_data.size > 0) {
@@ -664,17 +662,20 @@ void fiq_record(void)
 #if SAMPLE_SIZE == 16
         *dma_rec_data.p16++ = IISFIFO_RD;
 #elif SAMPLE_SIZE == 32
-        *dma_rec_data.p32++ = IISFIFO_RD >> 16;
-        *dma_rec_data.p32++ = IISFIFO_RD >> 16;
+        *dma_rec_data.p32++ = IISFIFO_RDH;
+        *dma_rec_data.p32++ = IISFIFO_RDH;
 #endif
         dma_rec_data.size -= 4;
     }
 
-    pcm_rec_more_ready_callback(0, (void *)&dma_rec_data.addr,
-                                &dma_rec_data.size);
+    if (pcm_rec_dma_complete_callback(PCM_DMAST_OK, &dma_rec_data.p_w,
+                                      &dma_rec_data.size))
+    {
+        pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
+    }
 }
 
-#endif /* SANSA_E200 */
+#endif /* SANSA_C200 || SANSA_E200 */
 
 void pcm_rec_dma_stop(void)
 {