Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit).

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 3 insertions, 3 deletions

diff --git a/firmware/target/arm/pcm-pp.c b/firmware/target/arm/pcm-pp.c
index 433e6e1e4f..64c6d0cdc8 100644
--- a/firmware/target/arm/pcm-pp.c
+++ b/firmware/target/arm/pcm-pp.c
@@ -72,7 +72,7 @@ void fiq_handler(void)
 /****************************************************************************
  ** Playback DMA transfer
  **/
-struct dma_data dma_play_data NOCACHEBSS_ATTR =
+struct dma_data dma_play_data SHAREDBSS_ATTR =
 {
     /* Initialize to a locked, stopped state */
     .p = NULL,
@@ -84,7 +84,7 @@ struct dma_data dma_play_data NOCACHEBSS_ATTR =
     .state = 0
 };
 
-static unsigned long pcm_freq NOCACHEDATA_ATTR = HW_SAMPR_DEFAULT; /* 44.1 is default */
+static unsigned long pcm_freq SHAREDDATA_ATTR = HW_SAMPR_DEFAULT; /* 44.1 is default */
 #ifdef HAVE_WM8751
 /* Samplerate control for audio codec */
 static int sr_ctrl = MROBE100_44100HZ;
@@ -356,7 +356,7 @@ const void * pcm_play_dma_get_peak_buffer(int *count)
  **/
 #ifdef HAVE_RECORDING
 /* PCM recording interrupt routine lockout */
-static struct dma_data dma_rec_data NOCACHEBSS_ATTR =
+static struct dma_data dma_rec_data SHAREDBSS_ATTR =
 {
     /* Initialize to a locked, stopped state */
     .p = NULL,