Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit).

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 2 insertions, 0 deletions

diff --git a/firmware/target/arm/olympus/boot.lds b/firmware/target/arm/olympus/boot.lds
index 5fbe999333..2c0245072c 100644
--- a/firmware/target/arm/olympus/boot.lds
+++ b/firmware/target/arm/olympus/boot.lds
@@ -27,6 +27,7 @@ SECTIONS
     *(.irodata)
     *(.idata)
     *(.data*)
+    *(.ncdata*)
     _dataend = . ;
    }
 
@@ -48,6 +49,7 @@ SECTIONS
      _edata = .;
      *(.bss*);
      *(.ibss);
+     *(.ncbss*);
      _end = .;
    }
 }