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authorMichael Sevakis <jethead71@rockbox.org>2008-04-06 04:34:57 +0000
committerMichael Sevakis <jethead71@rockbox.org>2008-04-06 04:34:57 +0000
commit05099149f193cac0c81b0129c17feb78b1a9681a (patch)
tree3dd5494dd494bcb4490ddcedef99e9f3a895cd3f /firmware/target/arm/iriver
parentbe698f086de4641a45dffd9289671588c2391a3c (diff)
downloadrockbox-05099149f193cac0c81b0129c17feb78b1a9681a.tar.gz
rockbox-05099149f193cac0c81b0129c17feb78b1a9681a.zip
Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/iriver')
-rw-r--r--firmware/target/arm/iriver/app.lds56
-rw-r--r--firmware/target/arm/iriver/boot.lds2
-rw-r--r--firmware/target/arm/iriver/h10/lcd-h10_20gb.c2
3 files changed, 49 insertions, 11 deletions
diff --git a/firmware/target/arm/iriver/app.lds b/firmware/target/arm/iriver/app.lds
index 765a5f0389..54af494d72 100644
--- a/firmware/target/arm/iriver/app.lds
+++ b/firmware/target/arm/iriver/app.lds
@@ -21,6 +21,14 @@ INPUT(target/arm/crt0-pp.o)
21#define IRAMORIG 0x40000000 21#define IRAMORIG 0x40000000
22#define IRAMSIZE 0xc000 22#define IRAMSIZE 0xc000
23 23
24#ifdef CPU_PP502x
25#define NOCACHE_BASE 0x10000000
26#else
27#define NOCACHE_BASE 0x28000000
28#endif
29
30#define CACHEALIGN_SIZE 16
31
24/* End of the audio buffer, where the codec buffer starts */ 32/* End of the audio buffer, where the codec buffer starts */
25#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) 33#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
26 34
@@ -70,6 +78,18 @@ SECTIONS
70 _dataend = .; 78 _dataend = .;
71 } > DRAM 79 } > DRAM
72 80
81#if NOCACHE_BASE != 0
82 /* .ncdata section is placed at uncached physical alias address and is
83 * loaded at the proper cached virtual address - no copying is
84 * performed in the init code */
85 .ncdata . + NOCACHE_BASE :
86 {
87 . = ALIGN(CACHEALIGN_SIZE);
88 *(.ncdata*)
89 . = ALIGN(CACHEALIGN_SIZE);
90 } AT> DRAM
91#endif
92
73 /DISCARD/ : 93 /DISCARD/ :
74 { 94 {
75 *(.eh_frame) 95 *(.eh_frame)
@@ -103,7 +123,7 @@ SECTIONS
103 _iend = .; 123 _iend = .;
104 } > IRAM 124 } > IRAM
105 125
106 .idle_stacks : 126 .idle_stacks (NOLOAD) :
107 { 127 {
108 *(.idle_stacks) 128 *(.idle_stacks)
109#if NUM_CORES > 1 129#if NUM_CORES > 1
@@ -116,7 +136,7 @@ SECTIONS
116 cop_idlestackend = .; 136 cop_idlestackend = .;
117 } > IRAM 137 } > IRAM
118 138
119 .stack : 139 .stack (NOLOAD) :
120 { 140 {
121 *(.stack) 141 *(.stack)
122 stackbegin = .; 142 stackbegin = .;
@@ -124,37 +144,53 @@ SECTIONS
124 stackend = .; 144 stackend = .;
125 } > IRAM 145 } > IRAM
126 146
127 .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors): 147 /* .bss and .ncbss are treated as a single section to use one init loop to
148 * zero it - note "_edata" and "_end" */
149 .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
150 SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
128 { 151 {
129 _edata = .; 152 _edata = .;
130 *(.bss*) 153 *(.bss*)
131 *(COMMON) 154 *(COMMON)
132 . = ALIGN(0x4); 155 . = ALIGN(0x4);
133 _end = .;
134 } > DRAM 156 } > DRAM
135 157
136 .audiobuf ALIGN(4) : 158#if NOCACHE_BASE != 0
159 .ncbss . + NOCACHE_BASE (NOLOAD):
160 {
161 . = ALIGN(CACHEALIGN_SIZE);
162 *(.ncbss*)
163 . = ALIGN(CACHEALIGN_SIZE);
164 } AT> DRAM
165#endif
166
167 /* This will be aligned by preceding alignments */
168 .endaddr . - NOCACHE_BASE (NOLOAD) :
169 {
170 _end = .;
171 } > DRAM
172
173 .audiobuf (NOLOAD) :
137 { 174 {
138 _audiobuffer = .; 175 _audiobuffer = .;
139 audiobuffer = .; 176 audiobuffer = .;
140 } > DRAM 177 } > DRAM
141 178
142 .audiobufend ENDAUDIOADDR: 179 .audiobufend ENDAUDIOADDR (NOLOAD) :
143 { 180 {
144 audiobufend = .; 181 audiobufend = .;
145 _audiobufend = .; 182 _audiobufend = .;
146 } > DRAM 183 } > DRAM
147 184
148 .codec ENDAUDIOADDR: 185 .codec ENDAUDIOADDR (NOLOAD) :
149 { 186 {
150 codecbuf = .; 187 codecbuf = .;
151 _codecbuf = .; 188 _codecbuf = .;
152 } 189 }
153 190
154 .plugin ENDADDR: 191 .plugin ENDADDR (NOLOAD) :
155 { 192 {
156 _pluginbuf = .; 193 _pluginbuf = .;
157 pluginbuf = .; 194 pluginbuf = .;
158 } 195 }
159} 196}
160
diff --git a/firmware/target/arm/iriver/boot.lds b/firmware/target/arm/iriver/boot.lds
index 5fbe999333..971ec6627b 100644
--- a/firmware/target/arm/iriver/boot.lds
+++ b/firmware/target/arm/iriver/boot.lds
@@ -27,6 +27,7 @@ SECTIONS
27 *(.irodata) 27 *(.irodata)
28 *(.idata) 28 *(.idata)
29 *(.data*) 29 *(.data*)
30 *(.ncdata*);
30 _dataend = . ; 31 _dataend = . ;
31 } 32 }
32 33
@@ -48,6 +49,7 @@ SECTIONS
48 _edata = .; 49 _edata = .;
49 *(.bss*); 50 *(.bss*);
50 *(.ibss); 51 *(.ibss);
52 *(.ncbss*);
51 _end = .; 53 _end = .;
52 } 54 }
53} 55}
diff --git a/firmware/target/arm/iriver/h10/lcd-h10_20gb.c b/firmware/target/arm/iriver/h10/lcd-h10_20gb.c
index 1c4116d2e7..1ee43c390f 100644
--- a/firmware/target/arm/iriver/h10/lcd-h10_20gb.c
+++ b/firmware/target/arm/iriver/h10/lcd-h10_20gb.c
@@ -34,7 +34,7 @@ static unsigned short disp_control_rev;
34/* Contrast setting << 8 */ 34/* Contrast setting << 8 */
35static int lcd_contrast; 35static int lcd_contrast;
36 36
37static unsigned lcd_yuv_options NOCACHEBSS_ATTR = 0; 37static unsigned lcd_yuv_options SHAREDBSS_ATTR = 0;
38 38
39/* Forward declarations */ 39/* Forward declarations */
40static void lcd_display_off(void); 40static void lcd_display_off(void);