diff options
author | Michael Sevakis <jethead71@rockbox.org> | 2009-01-23 01:23:25 +0000 |
---|---|---|
committer | Michael Sevakis <jethead71@rockbox.org> | 2009-01-23 01:23:25 +0000 |
commit | 7bcfc38b4216b73afaeffec506a83debb7e58df2 (patch) | |
tree | 8904a1a2ccc27f3eabc1a8c64fee91ea3dcf1f10 /firmware/target/arm/imx31/gigabeat-s/system-imx31.c | |
parent | da76a3469437261bd8857c6eddeaafcc601f373e (diff) | |
download | rockbox-7bcfc38b4216b73afaeffec506a83debb7e58df2.tar.gz rockbox-7bcfc38b4216b73afaeffec506a83debb7e58df2.zip |
Gigabeat S: Implement a genuine udelay function. Timer is gated to not run in WFI mode to save power and as such time until rollover is variable.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19820 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/system-imx31.c')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/system-imx31.c | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c index c339f4fe7c..7454806d07 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-imx31.c +++ b/firmware/target/arm/imx31/gigabeat-s/system-imx31.c | |||
@@ -32,6 +32,8 @@ | |||
32 | #include "clkctl-imx31.h" | 32 | #include "clkctl-imx31.h" |
33 | #include "mc13783.h" | 33 | #include "mc13783.h" |
34 | 34 | ||
35 | /** Watchdog timer routines **/ | ||
36 | |||
35 | /* Initialize the watchdog timer */ | 37 | /* Initialize the watchdog timer */ |
36 | void watchdog_init(unsigned int half_seconds) | 38 | void watchdog_init(unsigned int half_seconds) |
37 | { | 39 | { |
@@ -57,6 +59,33 @@ void watchdog_service(void) | |||
57 | WDOG_WSR = 0xaaaa; | 59 | WDOG_WSR = 0xaaaa; |
58 | } | 60 | } |
59 | 61 | ||
62 | /** GPT timer routines - basis for udelay **/ | ||
63 | |||
64 | /* Start the general-purpose timer (1MHz) */ | ||
65 | void gpt_start(void) | ||
66 | { | ||
67 | imx31_clkctl_module_clock_gating(CG_GPT, CGM_ON_RUN_WAIT); | ||
68 | unsigned int ipg_mhz = imx31_clkctl_get_ipg_clk() / 1000000; | ||
69 | |||
70 | GPTCR &= ~GPTCR_EN; /* Disable counter */ | ||
71 | GPTCR |= GPTCR_SWR; /* Reset module */ | ||
72 | while (GPTCR & GPTCR_SWR); | ||
73 | /* No output | ||
74 | * No capture | ||
75 | * Enable in run mode only (doesn't tick while in WFI) | ||
76 | * Freerun mode (count to 0xFFFFFFFF and roll-over to 0x00000000) | ||
77 | */ | ||
78 | GPTCR = GPTCR_FRR | GPTCR_CLKSRC_IPG_CLK; | ||
79 | GPTPR = ipg_mhz - 1; | ||
80 | GPTCR |= GPTCR_EN; | ||
81 | } | ||
82 | |||
83 | /* Stop the general-purpose timer */ | ||
84 | void gpt_stop(void) | ||
85 | { | ||
86 | GPTCR &= ~GPTCR_EN; | ||
87 | } | ||
88 | |||
60 | int system_memory_guard(int newmode) | 89 | int system_memory_guard(int newmode) |
61 | { | 90 | { |
62 | (void)newmode; | 91 | (void)newmode; |
@@ -84,7 +113,6 @@ void system_init(void) | |||
84 | /* CGR0 */ | 113 | /* CGR0 */ |
85 | CG_SD_MMC1, | 114 | CG_SD_MMC1, |
86 | CG_SD_MMC2, | 115 | CG_SD_MMC2, |
87 | CG_GPT, | ||
88 | CG_IIM, | 116 | CG_IIM, |
89 | CG_SDMA, | 117 | CG_SDMA, |
90 | CG_CSPI3, | 118 | CG_CSPI3, |
@@ -140,6 +168,7 @@ void system_init(void) | |||
140 | imx31_clkctl_module_clock_gating(disable_clocks[i], CGM_OFF); | 168 | imx31_clkctl_module_clock_gating(disable_clocks[i], CGM_OFF); |
141 | 169 | ||
142 | avic_init(); | 170 | avic_init(); |
171 | gpt_start(); | ||
143 | gpio_init(); | 172 | gpio_init(); |
144 | } | 173 | } |
145 | 174 | ||