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authorMichael Sevakis <jethead71@rockbox.org>2010-05-06 03:23:51 +0000
committerMichael Sevakis <jethead71@rockbox.org>2010-05-06 03:23:51 +0000
commita36a498c577ae5c9daa8487c8440df46d325bab3 (patch)
treeba8a35620ee10da2a7e1d6e6ed9234f0f35647d9 /firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h
parent8fd3ec97271001d0b50d4404f5891c9a4e77d960 (diff)
downloadrockbox-a36a498c577ae5c9daa8487c8440df46d325bab3.tar.gz
rockbox-a36a498c577ae5c9daa8487c8440df46d325bab3.zip
i.MX31/Gigabeat S: This should fix stability problems. One problem was to start using the DVFS controller properly so that interrupts will be masked at the lowest and highest frequency indexes. Millions of useless interrupts were occurring at 132MHz because its index was 2, not 3, which masks it automatically when it can't go slower. Stopping the flood was enough to actually see the difference in general. IRQ must be disabled when fiddling with the CCM registers and only enabled when waiting for voltage ramp as having them enables also causes spurious DVFS ints. Implement interruptible ISR pro/epilogue more safely (always using IRQ stack even in SVC mode handling). Fix an improper inequality in DVFS code (which set regs for down when going up and v.v.). Misc. support changes. Have internal tables take less RAM.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25837 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h')
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h224
1 files changed, 99 insertions, 125 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h b/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h
index 4876736a2b..7fc7b56dff 100644
--- a/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/dvfs_dptc_tables-target.h
@@ -24,12 +24,12 @@
24#define _DVFS_DPTC_TARGET_H_ 24#define _DVFS_DPTC_TARGET_H_
25 25
26#define DVFS_LEVEL_DEFAULT 1 /* 264 MHz - safe frequency for 1.35V */ 26#define DVFS_LEVEL_DEFAULT 1 /* 264 MHz - safe frequency for 1.35V */
27#define DVFS_NUM_LEVELS 3 /* 528 MHz, 264 MHz, 132 MHz */
28#define DVFS_NO_PWRRDY /* PWRRDY is connected to different SoC port */ 27#define DVFS_NO_PWRRDY /* PWRRDY is connected to different SoC port */
28#define DVFS_LEVEL_MASK (DVFS_LEVEL_0 | DVFS_LEVEL_1 | DVFS_LEVEL_3)
29 29
30#define DPTC_WP_DEFAULT 1 /* 1.600, 1.350, 1.350 */ 30#define DPTC_WP_DEFAULT 1 /* 1.600, 1.350, 1.350 */
31#define DPTC_WP_PANIC 3 /* Up to minimum for > 400 MHz */ 31#define DPTC_WP_PANIC 3 /* Up to minimum for > 400 MHz */
32#define DPTC_NUM_WP 17 32
33 33
34#define VOLTAGE_SETTING_MIN MC13783_SW_1_350 34#define VOLTAGE_SETTING_MIN MC13783_SW_1_350
35#define VOLTAGE_SETTING_MAX MC13783_SW_1_625 35#define VOLTAGE_SETTING_MAX MC13783_SW_1_625
@@ -54,7 +54,7 @@
54 * and the values have an additional division or the comments in the BSP are 54 * and the values have an additional division or the comments in the BSP are
55 * incorrect. 55 * incorrect.
56 */ 56 */
57#define DVFS_DIV3CK CCM_LTR0_DIV3CK_131072 57#define DVFS_DIV3CK 0x3
58 58
59/* UPCNT defines the amount of times the up threshold should be exceeded 59/* UPCNT defines the amount of times the up threshold should be exceeded
60 * before DVFS will trigger frequency increase request. */ 60 * before DVFS will trigger frequency increase request. */
@@ -109,146 +109,120 @@ dvfs_dptc_voltage_table[DPTC_NUM_WP] =
109 { { MC13783_SW_1_225, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } }, 109 { { MC13783_SW_1_225, MC13783_SW_1_350, MC13783_SW_1_350, MC13783_SW_1_350 } },
110}; 110};
111 111
112#if 1 112#if CONFIG_CKIH_FREQ == 27000000
113/* For 27 MHz PLL reference clock */ 113/* For 27 MHz PLL reference clock */
114static const struct dptc_dcvr_table_entry 114static const struct dptc_dcvr_table_entry
115dptc_dcvr_table[DVFS_NUM_LEVELS][DPTC_NUM_WP] = 115dptc_dcvr_table_0[DPTC_NUM_WP] =
116{ 116 /* DCVR0 DCVR1 DCVR2 DCVR3 */
117 /* DCVR0 DCVR1 DCVR2 DCVR3 */ 117{ /* 528 MHz */
118 { /* 528 MHz */ 118 { 0xffc00000, 0x90400000, 0xffc00000, 0xdd000000 },
119 { 0xffc00000, 0x90400000, 0xffc00000, 0xdd000000 }, 119 { 0xffc00000, 0x90629890, 0xffc00000, 0xdd34ed20 },
120 { 0xffc00000, 0x90629890, 0xffc00000, 0xdd34ed20 }, 120 { 0xffc00000, 0x90629890, 0xffc00000, 0xdd34ed20 },
121 { 0xffc00000, 0x90629890, 0xffc00000, 0xdd34ed20 }, 121 { 0xffc00000, 0x90629894, 0xffc00000, 0xdd74fd24 },
122 { 0xffc00000, 0x90629894, 0xffc00000, 0xdd74fd24 }, 122 { 0xffc00000, 0x90a2a894, 0xffc00000, 0xddb50d28 },
123 { 0xffc00000, 0x90a2a894, 0xffc00000, 0xddb50d28 }, 123 { 0xffc00000, 0x90e2b89c, 0xffc00000, 0xde352d30 },
124 { 0xffc00000, 0x90e2b89c, 0xffc00000, 0xde352d30 }, 124 { 0xffc00000, 0x9162d8a0, 0xffc00000, 0xdef55d38 },
125 { 0xffc00000, 0x9162d8a0, 0xffc00000, 0xdef55d38 }, 125 { 0xffc00000, 0x91e2f8a8, 0xffc00000, 0xdfb58d44 },
126 { 0xffc00000, 0x91e2f8a8, 0xffc00000, 0xdfb58d44 }, 126 { 0xffc00000, 0x926308b0, 0xffc00000, 0xe0b5cd54 },
127 { 0xffc00000, 0x926308b0, 0xffc00000, 0xe0b5cd54 }, 127 { 0xffc00000, 0x92e328bc, 0xffc00000, 0xe1f60d64 },
128 { 0xffc00000, 0x92e328bc, 0xffc00000, 0xe1f60d64 }, 128 { 0xffc00000, 0x93a358c0, 0xffc00000, 0xe3365d74 },
129 { 0xffc00000, 0x93a358c0, 0xffc00000, 0xe3365d74 }, 129 { 0xffc00000, 0xf66388cc, 0xffc00000, 0xf6768d84 },
130 { 0xffc00000, 0xf66388cc, 0xffc00000, 0xf6768d84 }, 130 { 0xffc00000, 0xf663b8d4, 0xffc00000, 0xf676dd98 },
131 { 0xffc00000, 0xf663b8d4, 0xffc00000, 0xf676dd98 }, 131 { 0xffc00000, 0xf663e8e0, 0xffc00000, 0xf6773da4 },
132 { 0xffc00000, 0xf663e8e0, 0xffc00000, 0xf6773da4 }, 132 { 0xffc00000, 0xf66418ec, 0xffc00000, 0xf6778dbc },
133 { 0xffc00000, 0xf66418ec, 0xffc00000, 0xf6778dbc }, 133 { 0xffc00000, 0xf66458fc, 0xffc00000, 0xf677edd0 },
134 { 0xffc00000, 0xf66458fc, 0xffc00000, 0xf677edd0 }, 134 { 0xffc00000, 0xf6648908, 0xffc00000, 0xf6783de8 },
135 { 0xffc00000, 0xf6648908, 0xffc00000, 0xf6783de8 }, 135};
136 136
137 }, 137static const struct dptc_dcvr_table_entry
138 { /* 264 MHz */ 138dptc_dcvr_table_1_3[DPTC_NUM_WP] =
139 { 0xffc00000, 0x90400000, 0xffc00000, 0xdd000000 }, 139 /* DCVR0 DCVR1 DCVR2 DCVR3 */
140 { 0xffc00000, 0x9048a224, 0xffc00000, 0xdd0d4348 }, 140{ /* 264 MHz, 132 MHz */
141 { 0xffc00000, 0x9048a224, 0xffc00000, 0xdd0d4348 }, 141 { 0xffc00000, 0x90400000, 0xffc00000, 0xdd000000 },
142 { 0xffc00000, 0x9048a224, 0xffc00000, 0xdd4d4348 }, 142 { 0xffc00000, 0x9048a224, 0xffc00000, 0xdd0d4348 },
143 { 0xffc00000, 0x9088b228, 0xffc00000, 0xdd8d434c }, 143 { 0xffc00000, 0x9048a224, 0xffc00000, 0xdd0d4348 },
144 { 0xffc00000, 0x90c8b228, 0xffc00000, 0xde0d534c }, 144 { 0xffc00000, 0x9048a224, 0xffc00000, 0xdd4d4348 },
145 { 0xffc00000, 0x9148b228, 0xffc00000, 0xdecd5350 }, 145 { 0xffc00000, 0x9088b228, 0xffc00000, 0xdd8d434c },
146 { 0xffc00000, 0x91c8c22c, 0xffc00000, 0xdf8d6354 }, 146 { 0xffc00000, 0x90c8b228, 0xffc00000, 0xde0d534c },
147 { 0xffc00000, 0x9248d22c, 0xffc00000, 0xe08d7354 }, 147 { 0xffc00000, 0x9148b228, 0xffc00000, 0xdecd5350 },
148 { 0xffc00000, 0x92c8d230, 0xffc00000, 0xe1cd8358 }, 148 { 0xffc00000, 0x91c8c22c, 0xffc00000, 0xdf8d6354 },
149 { 0xffc00000, 0x9388e234, 0xffc00000, 0xe30d935c }, 149 { 0xffc00000, 0x9248d22c, 0xffc00000, 0xe08d7354 },
150 { 0xffc00000, 0xf648e234, 0xffc00000, 0xf64db364 }, 150 { 0xffc00000, 0x92c8d230, 0xffc00000, 0xe1cd8358 },
151 { 0xffc00000, 0xf648f238, 0xffc00000, 0xf64dc368 }, 151 { 0xffc00000, 0x9388e234, 0xffc00000, 0xe30d935c },
152 { 0xffc00000, 0xf648f23c, 0xffc00000, 0xf64dd36c }, 152 { 0xffc00000, 0xf648e234, 0xffc00000, 0xf64db364 },
153 { 0xffc00000, 0xf649023c, 0xffc00000, 0xf64de370 }, 153 { 0xffc00000, 0xf648f238, 0xffc00000, 0xf64dc368 },
154 { 0xffc00000, 0xf649123c, 0xffc00000, 0xf64df374 }, 154 { 0xffc00000, 0xf648f23c, 0xffc00000, 0xf64dd36c },
155 { 0xffc00000, 0xf6492240, 0xffc00000, 0xf64e1378 }, 155 { 0xffc00000, 0xf649023c, 0xffc00000, 0xf64de370 },
156 { 0xffc00000, 0xf649123c, 0xffc00000, 0xf64df374 },
157 { 0xffc00000, 0xf6492240, 0xffc00000, 0xf64e1378 },
156 158
157 },
158 { /* 132 MHz */
159 { 0xffc00000, 0x90400000, 0xffc00000, 0xdd000000 },
160 { 0xffc00000, 0x9048a224, 0xffc00000, 0xdd0d4348 },
161 { 0xffc00000, 0x9048a224, 0xffc00000, 0xdd0d4348 },
162 { 0xffc00000, 0x9048a224, 0xffc00000, 0xdd4d4348 },
163 { 0xffc00000, 0x9088b228, 0xffc00000, 0xdd8d434c },
164 { 0xffc00000, 0x90c8b228, 0xffc00000, 0xde0d534c },
165 { 0xffc00000, 0x9148b228, 0xffc00000, 0xdecd5350 },
166 { 0xffc00000, 0x91c8c22c, 0xffc00000, 0xdf8d6354 },
167 { 0xffc00000, 0x9248d22c, 0xffc00000, 0xe08d7354 },
168 { 0xffc00000, 0x92c8d230, 0xffc00000, 0xe1cd8358 },
169 { 0xffc00000, 0x9388e234, 0xffc00000, 0xe30d935c },
170 { 0xffc00000, 0xf648e234, 0xffc00000, 0xf64db364 },
171 { 0xffc00000, 0xf648f238, 0xffc00000, 0xf64dc368 },
172 { 0xffc00000, 0xf648f23c, 0xffc00000, 0xf64dd36c },
173 { 0xffc00000, 0xf649023c, 0xffc00000, 0xf64de370 },
174 { 0xffc00000, 0xf649123c, 0xffc00000, 0xf64df374 },
175 { 0xffc00000, 0xf6492240, 0xffc00000, 0xf64e1378 },
176 },
177}; 159};
178#else/* For 26 MHz PLL reference clock */ 160#else/* For 26 MHz PLL reference clock */
179static const struct dptc_dcvr_table_entry 161static const struct dptc_dcvr_table_entry
180dptc_dcvr_table[DVFS_NUM_LEVELS][DPTC_NUM_WP] = 162dptc_dcvr_table_0[DPTC_NUM_WP] =
181{ 163 /* DCVR0 DCVR1 DCVR2 DCVR3 */
182 /* DCVR0 DCVR1 DCVR2 DCVR3 */ 164{ /* 528 MHz */
183 { /* 528 MHz */ 165 { 0xffc00000, 0x95c00000, 0xffc00000, 0xe5800000 },
184 { 0xffc00000, 0x95c00000, 0xffc00000, 0xe5800000 }, 166 { 0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0 },
185 { 0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0 }, 167 { 0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0 },
186 { 0xffc00000, 0x95e3e8e4, 0xffc00000, 0xe5b6fda0 }, 168 { 0xffc00000, 0x95e3e8e8, 0xffc00000, 0xe5f70da4 },
187 { 0xffc00000, 0x95e3e8e8, 0xffc00000, 0xe5f70da4 }, 169 { 0xffc00000, 0x9623f8e8, 0xffc00000, 0xe6371da8 },
188 { 0xffc00000, 0x9623f8e8, 0xffc00000, 0xe6371da8 }, 170 { 0xffc00000, 0x966408f0, 0xffc00000, 0xe6b73db0 },
189 { 0xffc00000, 0x966408f0, 0xffc00000, 0xe6b73db0 }, 171 { 0xffc00000, 0x96e428f4, 0xffc00000, 0xe7776dbc },
190 { 0xffc00000, 0x96e428f4, 0xffc00000, 0xe7776dbc }, 172 { 0xffc00000, 0x976448fc, 0xffc00000, 0xe8379dc8 },
191 { 0xffc00000, 0x976448fc, 0xffc00000, 0xe8379dc8 }, 173 { 0xffc00000, 0x97e46904, 0xffc00000, 0xe977ddd8 },
192 { 0xffc00000, 0x97e46904, 0xffc00000, 0xe977ddd8 }, 174 { 0xffc00000, 0x98a48910, 0xffc00000, 0xeab81de8 },
193 { 0xffc00000, 0x98a48910, 0xffc00000, 0xeab81de8 }, 175 { 0xffc00000, 0x9964b918, 0xffc00000, 0xebf86df8 },
194 { 0xffc00000, 0x9964b918, 0xffc00000, 0xebf86df8 }, 176 { 0xffc00000, 0xffe4e924, 0xffc00000, 0xfff8ae08 },
195 { 0xffc00000, 0xffe4e924, 0xffc00000, 0xfff8ae08 }, 177 { 0xffc00000, 0xffe5192c, 0xffc00000, 0xfff8fe1c },
196 { 0xffc00000, 0xffe5192c, 0xffc00000, 0xfff8fe1c }, 178 { 0xffc00000, 0xffe54938, 0xffc00000, 0xfff95e2c },
197 { 0xffc00000, 0xffe54938, 0xffc00000, 0xfff95e2c }, 179 { 0xffc00000, 0xffe57944, 0xffc00000, 0xfff9ae44 },
198 { 0xffc00000, 0xffe57944, 0xffc00000, 0xfff9ae44 }, 180 { 0xffc00000, 0xffe5b954, 0xffc00000, 0xfffa0e58 },
199 { 0xffc00000, 0xffe5b954, 0xffc00000, 0xfffa0e58 }, 181 { 0xffc00000, 0xffe5e960, 0xffc00000, 0xfffa6e70 },
200 { 0xffc00000, 0xffe5e960, 0xffc00000, 0xfffa6e70 }, 182};
201 }, 183
202 { /* 264 MHz */ 184static const struct dptc_dcvr_table_entry
203 { 0xffc00000, 0x95c00000, 0xffc00000, 0xe5800000 }, 185dptc_dcvr_table_1_3[DPTC_NUM_WP] =
204 { 0xffc00000, 0x95c8f238, 0xffc00000, 0xe58dc368 }, 186 /* DCVR0 DCVR1 DCVR2 DCVR3 */
205 { 0xffc00000, 0x95c8f238, 0xffc00000, 0xe58dc368 }, 187{ /* 264 MHz, 132 MHz */
206 { 0xffc00000, 0x95c8f238, 0xffc00000, 0xe5cdc368 }, 188 { 0xffc00000, 0x95c00000, 0xffc00000, 0xe5800000 },
207 { 0xffc00000, 0x9609023c, 0xffc00000, 0xe60dc36c }, 189 { 0xffc00000, 0x95c8f238, 0xffc00000, 0xe58dc368 },
208 { 0xffc00000, 0x9649023c, 0xffc00000, 0xe68dd36c }, 190 { 0xffc00000, 0x95c8f238, 0xffc00000, 0xe58dc368 },
209 { 0xffc00000, 0x96c9023c, 0xffc00000, 0xe74dd370 }, 191 { 0xffc00000, 0x95c8f238, 0xffc00000, 0xe5cdc368 },
210 { 0xffc00000, 0x97491240, 0xffc00000, 0xe80de374 }, 192 { 0xffc00000, 0x9609023c, 0xffc00000, 0xe60dc36c },
211 { 0xffc00000, 0x97c92240, 0xffc00000, 0xe94df374 }, 193 { 0xffc00000, 0x9649023c, 0xffc00000, 0xe68dd36c },
212 { 0xffc00000, 0x98892244, 0xffc00000, 0xea8e0378 }, 194 { 0xffc00000, 0x96c9023c, 0xffc00000, 0xe74dd370 },
213 { 0xffc00000, 0x99493248, 0xffc00000, 0xebce137c }, 195 { 0xffc00000, 0x97491240, 0xffc00000, 0xe80de374 },
214 { 0xffc00000, 0xffc93248, 0xffc00000, 0xffce3384 }, 196 { 0xffc00000, 0x97c92240, 0xffc00000, 0xe94df374 },
215 { 0xffc00000, 0xffc9424c, 0xffc00000, 0xffce4388 }, 197 { 0xffc00000, 0x98892244, 0xffc00000, 0xea8e0378 },
216 { 0xffc00000, 0xffc95250, 0xffc00000, 0xffce538c }, 198 { 0xffc00000, 0x99493248, 0xffc00000, 0xebce137c },
217 { 0xffc00000, 0xffc96250, 0xffc00000, 0xffce7390 }, 199 { 0xffc00000, 0xffc93248, 0xffc00000, 0xffce3384 },
218 { 0xffc00000, 0xffc97254, 0xffc00000, 0xffce8394 }, 200 { 0xffc00000, 0xffc9424c, 0xffc00000, 0xffce4388 },
219 { 0xffc00000, 0xffc98258, 0xffc00000, 0xffcea39c }, 201 { 0xffc00000, 0xffc95250, 0xffc00000, 0xffce538c },
220 }, 202 { 0xffc00000, 0xffc96250, 0xffc00000, 0xffce7390 },
221 { /* 132 MHz */ 203 { 0xffc00000, 0xffc97254, 0xffc00000, 0xffce8394 },
222 { 0xffc00000, 0x95c00000, 0xffc00000, 0xe5800000 }, 204 { 0xffc00000, 0xffc98258, 0xffc00000, 0xffcea39c },
223 { 0xffc00000, 0x95c8f238, 0xffc00000, 0xe58dc368 },
224 { 0xffc00000, 0x95c8f238, 0xffc00000, 0xe58dc368 },
225 { 0xffc00000, 0x95c8f238, 0xffc00000, 0xe5cdc368 },
226 { 0xffc00000, 0x9609023c, 0xffc00000, 0xe60dc36c },
227 { 0xffc00000, 0x9649023c, 0xffc00000, 0xe68dd36c },
228 { 0xffc00000, 0x96c9023c, 0xffc00000, 0xe74dd370 },
229 { 0xffc00000, 0x97491240, 0xffc00000, 0xe80de374 },
230 { 0xffc00000, 0x97c92240, 0xffc00000, 0xe94df374 },
231 { 0xffc00000, 0x98892244, 0xffc00000, 0xea8e0378 },
232 { 0xffc00000, 0x99493248, 0xffc00000, 0xebce137c },
233 { 0xffc00000, 0xffc93248, 0xffc00000, 0xffce3384 },
234 { 0xffc00000, 0xffc9424c, 0xffc00000, 0xffce4388 },
235 { 0xffc00000, 0xffc95250, 0xffc00000, 0xffce538c },
236 { 0xffc00000, 0xffc96250, 0xffc00000, 0xffce7390 },
237 { 0xffc00000, 0xffc97254, 0xffc00000, 0xffce8394 },
238 { 0xffc00000, 0xffc98258, 0xffc00000, 0xffcea39c },
239 },
240}; 205};
241#endif 206#endif
242 207
208static const struct dptc_dcvr_table_entry * const
209 dptc_dcvr_table [DVFS_NUM_LEVELS] =
210{
211 dptc_dcvr_table_0,
212 dptc_dcvr_table_1_3,
213 NULL,
214 dptc_dcvr_table_1_3,
215};
243 216
244/* For 27 MHz PLL reference clock */ 217/* For 27 MHz PLL reference clock */
245static const struct dvfs_clock_table_entry 218static const struct dvfs_clock_table_entry
246dvfs_clock_table[DVFS_NUM_LEVELS] = 219dvfs_clock_table[4] =
247{ 220{
248 /* PLL val PDR0 val PLL VSCNT */ 221 /* PLL val PDR0 val PLL VSCNT */
249 { 0x00082407, 0xff841e58, 1, 7 }, /* MCUPLL, 528 MHz, /1 = 528 MHz */ 222 { 0x00082407, 0xff841e58, 1, 7 }, /* MCUPLL, 528 MHz, /1 = 528 MHz */
250 { 0x00082407, 0xff841e59, 1, 7 }, /* MCUPLL, 528 MHz, /2 = 264 MHz */ 223 { 0x00082407, 0xff841e59, 1, 7 }, /* MCUPLL, 528 MHz, /2 = 264 MHz */
251 { 0x00082407, 0xff841e5b, 1, 7 }, /* MCUPLL, 528 MHz, /4 = 132 MHz */ 224 { 0x00082407, 0xff841e5b, 1, 7 }, /* MCUPLL, 528 MHz, /4 = 132 MHz */
225 { 0x00082407, 0xff841e5b, 1, 7 }, /* MCUPLL, 528 MHz, /4 = 132 MHz */
252}; 226};
253 227
254 228
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-14 06:20:37 +0000