diff options
author | Michael Sevakis <jethead71@rockbox.org> | 2008-02-05 04:43:19 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2008-02-05 04:43:19 +0000 |
commit | 1f021af60cd0351a309666c2e32b3d1b8b2cbd6f (patch) | |
tree | 88710bcc59d80831327b00d59af0eb6a6f758de6 /firmware/target/arm/imx31/gigabeat-s/avic-imx31.h | |
parent | 3f85a4bc97fb2120870fcd4a6650fd72d4a6338f (diff) | |
download | rockbox-1f021af60cd0351a309666c2e32b3d1b8b2cbd6f.tar.gz rockbox-1f021af60cd0351a309666c2e32b3d1b8b2cbd6f.zip |
Gigabeat S mixer: Make some progress. Get the tick and core sleep working using the AVIC. Redo the startup code to remap from IRAM and not include the lcd driver frambuffer in the remapping (until it can be moved). Clean up LCD driver. For other misc. changes, see the diffs. Now it progresses to ATA init and fails with -11 but without crashing or hanging. Replace all bootloaders.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16216 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/avic-imx31.h')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/avic-imx31.h | 124 |
1 files changed, 27 insertions, 97 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h index 53a37b353b..29a3ec8dd0 100644 --- a/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h +++ b/firmware/target/arm/imx31/gigabeat-s/avic-imx31.h | |||
@@ -19,107 +19,37 @@ | |||
19 | #ifndef AVIC_IMX31_H | 19 | #ifndef AVIC_IMX31_H |
20 | #define AVIC_IMX31_H | 20 | #define AVIC_IMX31_H |
21 | 21 | ||
22 | 22 | enum INT_TYPE | |
23 | enum INT_TYPE {IRQ=0,FIQ}; | 23 | { |
24 | 24 | IRQ = 0, | |
25 | struct int_names { | 25 | FIQ |
26 | char name[16]; | ||
27 | }; | 26 | }; |
28 | 27 | ||
29 | static const struct int_names imx31_int_names[64] = | 28 | enum IMX31_INT_LIST |
30 | { {"RESERVED0"}, | 29 | { |
31 | {"RESERVED1"}, | 30 | __IMX31_INT_FIRST = -1, |
32 | {"RESERVED2"}, | 31 | RESERVED0, RESERVED1, RESERVED2, I2C3, |
33 | {"I2C3"}, | 32 | I2C2, MPEG4_ENCODER, RTIC, FIR, |
34 | {"I2C2"}, | 33 | MMC_SDHC2, MMC_SDHC1, I2C1, SSI2, |
35 | {"MPEG4_ENCODER"}, | 34 | SSI1, CSPI2, CSPI1, ATA, |
36 | {"RTIC"}, | 35 | MBX, CSPI3, UART3, IIM, |
37 | {"FIR"}, | 36 | SIM1, SIM2, RNGA, EVTMON, |
38 | {"MMC/SDHC2"}, | 37 | KPP, RTC, PWN, EPIT2, |
39 | {"MMC/SDHC1"}, | 38 | EPIT1, GPT, PWR_FAIL, CCM_DVFS, |
40 | {"I2C1"}, | 39 | UART2, NANDFC, SDMA, USB_HOST1, |
41 | {"SSI2"}, | 40 | USB_HOST2, USB_OTG, RESERVED3, MSHC1, |
42 | {"SSI1"}, | 41 | MSHC2, IPU_ERR, IPU, RESERVED4, |
43 | {"CSPI2"}, | 42 | RESERVED5, UART1, UART4, UART5, |
44 | {"CSPI1"}, | 43 | ETC_IRQ, SCC_SCM, SCC_SMN, GPIO2, |
45 | {"ATA"}, | 44 | GPIO1, CCM_CLK, PCMCIA, WDOG, |
46 | {"MBX"}, | 45 | GPIO3, RESERVED6, EXT_PWMG, EXT_TEMP, |
47 | {"CSPI3"}, | 46 | EXT_SENS1, EXT_SENS2, EXT_WDOG, EXT_TV, |
48 | {"UART3"}, | 47 | ALL |
49 | {"IIM"}, | 48 | }; |
50 | {"SIM1"}, | ||
51 | {"SIM2"}, | ||
52 | {"RNGA"}, | ||
53 | {"EVTMON"}, | ||
54 | {"KPP"}, | ||
55 | {"RTC"}, | ||
56 | {"PWN"}, | ||
57 | {"EPIT2"}, | ||
58 | {"EPIT1"}, | ||
59 | {"GPT"}, | ||
60 | {"PWR_FAIL"}, | ||
61 | {"CCM_DVFS"}, | ||
62 | {"UART2"}, | ||
63 | {"NANDFC"}, | ||
64 | {"SDMA"}, | ||
65 | {"USB_HOST1"}, | ||
66 | {"USB_HOST2"}, | ||
67 | {"USB_OTG"}, | ||
68 | {"RESERVED3"}, | ||
69 | {"MSHC1"}, | ||
70 | {"MSHC2"}, | ||
71 | {"IPU_ERR"}, | ||
72 | {"IPU"}, | ||
73 | {"RESERVED4"}, | ||
74 | {"RESERVED5"}, | ||
75 | {"UART1"}, | ||
76 | {"UART4"}, | ||
77 | {"UART5"}, | ||
78 | {"ETC_IRQ"}, | ||
79 | {"SCC_SCM"}, | ||
80 | {"SCC_SMN"}, | ||
81 | {"GPIO2"}, | ||
82 | {"GPIO1"}, | ||
83 | {"CCM_CLK"}, | ||
84 | {"PCMCIA"}, | ||
85 | {"WDOG"}, | ||
86 | {"GPIO3"}, | ||
87 | {"RESERVED6"}, | ||
88 | {"EXT_PWMG"}, | ||
89 | {"EXT_TEMP"}, | ||
90 | {"EXT_SENS1"}, | ||
91 | {"EXT_SENS2"}, | ||
92 | {"EXT_WDOG"}, | ||
93 | {"EXT_TV"} }; | ||
94 | |||
95 | enum IMX31_INT_LIST { | ||
96 | RESERVED0 = 0,RESERVED1,RESERVED2,I2C3, | ||
97 | I2C2,MPEG4_ENCODER,RTIC,FIR,MMC_SDHC2, | ||
98 | MMC_SDHC1,I2C1,SSI2,SSI1,CSPI2,CSPI1, | ||
99 | ATA,MBX,CSPI3,UART3,IIM,SIM1,SIM2, | ||
100 | RNGA,EVTMON,KPP,RTC,PWN,EPIT2,EPIT1, | ||
101 | GPT,PWR_FAIL,CCM_DVFS,UART2,NANDFC, | ||
102 | SDMA,USB_HOST1,USB_HOST2,USB_OTG, | ||
103 | RESERVED3,MSHC1,MSHC2,IPU_ERR,IPU, | ||
104 | RESERVED4,RESERVED5,UART1,UART4,UART5, | ||
105 | ETC_IRQ,SCC_SCM,SCC_SMN,GPIO2,GPIO1, | ||
106 | CCM_CLK,PCMCIA,WDOG,GPIO3,RESERVED6, | ||
107 | EXT_PWMG,EXT_TEMP,EXT_SENS1,EXT_SENS2, | ||
108 | EXT_WDOG,EXT_TV,ALL }; | ||
109 | |||
110 | static struct avic_int { | ||
111 | char * name; | ||
112 | enum INT_TYPE int_type; | ||
113 | unsigned int addr; | ||
114 | unsigned int priority; | ||
115 | void (*pInt_Handler) (void); | ||
116 | } imx31_int[64]; | ||
117 | 49 | ||
118 | void avic_init(void); | 50 | void avic_init(void); |
119 | void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, | 51 | void avic_enable_int(enum IMX31_INT_LIST ints, enum INT_TYPE intstype, |
120 | void (*pInt_Handler) (void)); | 52 | void (*handler)(void)); |
121 | void avic_disable_int(enum IMX31_INT_LIST ints) ; | 53 | void avic_disable_int(enum IMX31_INT_LIST ints); |
122 | void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype); | 54 | void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype); |
123 | void Unhandled_Int(void); | ||
124 | void vector_init(void) __attribute__ ((section(".avic_int"),naked)); | ||
125 | #endif | 55 | #endif |