i.MX31/Gigabeat S: This should fix stability problems. One problem was to start using the DVFS controller properly so that interrupts will be masked at the lowest and highest frequency indexes. Millions of useless interrupts were occurring at 132MHz because its index was 2, not 3, which masks it automatically when it can't go slower. Stopping the flood was enough to actually see the difference in general. IRQ must be disabled when fiddling with the CCM registers and only enabled when waiting for voltage ramp as having them enables also causes spurious DVFS ints. Implement interruptible ISR pro/epilogue more safely (always using IRQ stack even in SVC mode handling). Fix an improper inequality in DVFS code (which set regs for down when going up and v.v.). Misc. support changes. Have internal tables take less RAM.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25837 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 10 insertions, 0 deletions

diff --git a/firmware/target/arm/imx31/dvfs_dptc-imx31.h b/firmware/target/arm/imx31/dvfs_dptc-imx31.h
index 2bf6114a11..844fd6ebff 100644
--- a/firmware/target/arm/imx31/dvfs_dptc-imx31.h
+++ b/firmware/target/arm/imx31/dvfs_dptc-imx31.h
@@ -107,6 +107,16 @@ struct dvfs_lt_signal_descriptor
     uint8_t detect   : 1; /* 1 = edge-detected */
 };
 
+#define DVFS_NUM_LEVELS 4
+#define DPTC_NUM_WP    17
+
+/* 0 and 3 are *required*. DVFS hardware depends upon DVSUP pins showing
+ * minimum (11) and maximum (00) levels or interrupts will be continuously
+ * asserted. */
+#define DVFS_LEVEL_0   (1u << 0)
+#define DVFS_LEVEL_1   (1u << 1)
+#define DVFS_LEVEL_2   (1u << 2)
+#define DVFS_LEVEL_3   (1u << 3)
 
 extern long cpu_voltage_setting;