i.MX31/Gigabeat S: This should fix stability problems. One problem was to start using the DVFS controller properly so that interrupts will be masked at the lowest and highest frequency indexes. Millions of useless interrupts were occurring at 132MHz because its index was 2, not 3, which masks it automatically when it can't go slower. Stopping the flood was enough to actually see the difference in general. IRQ must be disabled when fiddling with the CCM registers and only enabled when waiting for voltage ramp as having them enables also causes spurious DVFS ints. Implement interruptible ISR pro/epilogue more safely (always using IRQ stack even in SVC mode handling). Fix an improper inequality in DVFS code (which set regs for down when going up and v.v.). Misc. support changes. Have internal tables take less RAM.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25837 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 8 insertions, 4 deletions

diff --git a/firmware/target/arm/imx31/debug-imx31.c b/firmware/target/arm/imx31/debug-imx31.c
index 2c4f8b4023..783ba728a6 100644
--- a/firmware/target/arm/imx31/debug-imx31.c
+++ b/firmware/target/arm/imx31/debug-imx31.c
@@ -40,8 +40,10 @@ bool __dbg_hw_info(void)
     unsigned int freq;
     uint32_t regval;
 
-    extern volatile unsigned int dvfs_nr_dn, dvfs_nr_up, dvfs_nr_pnc;
-    extern volatile unsigned int dptc_nr_dn, dptc_nr_up, dptc_nr_pnc;
+    extern volatile unsigned int dvfs_nr_dn, dvfs_nr_up,
+                                 dvfs_nr_pnc, dvfs_nr_no;
+    extern volatile unsigned int dptc_nr_dn, dptc_nr_up,
+                                 dptc_nr_pnc, dptc_nr_no;
 
     lcd_clear_display();
     lcd_setfont(FONT_SYSFIXED);
@@ -119,13 +121,15 @@ bool __dbg_hw_info(void)
         lcd_putsf(0, line++, "cpu_frequency: %ld Hz", cpu_frequency);
 
         lcd_putsf(0, line++, "dvfs_level: %u", dvfs_get_level());
-        lcd_putsf(0, line++, "dvfs d|u|p: %u %u %u", dvfs_nr_dn, dvfs_nr_up, dvfs_nr_pnc);
+        lcd_putsf(0, line++, "dvfs d|u|p|n: %u %u %u %u",
+                  dvfs_nr_dn, dvfs_nr_up, dvfs_nr_pnc, dvfs_nr_no);
         regval = dvfs_dptc_get_voltage();
         lcd_putsf(0, line++, "cpu_voltage: %d.%03d V", regval / 1000,
                   regval % 1000);
 
         lcd_putsf(0, line++, "dptc_wp: %u", dptc_get_wp());
-        lcd_putsf(0, line++, "dptc d|u|p: %u %u %u", dptc_nr_dn, dptc_nr_up, dptc_nr_pnc);
+        lcd_putsf(0, line++, "dptc d|u|p|n: %u %u %u %u",
+                  dptc_nr_dn, dptc_nr_up, dptc_nr_pnc, dptc_nr_no);
         lcd_putsf(0, line++, "DVCR0,1: %08lX %08lX", CCM_DCVR0, CCM_DCVR1);
         lcd_putsf(0, line++, "DVCR2,3: %08lX %08lX", CCM_DCVR2, CCM_DCVR3);
         lcd_putsf(0, line++, "SWITCHERS0: %08lX", mc13783_read(MC13783_SWITCHERS0));