diff options
author | Michael Sevakis <jethead71@rockbox.org> | 2008-02-05 04:43:19 +0000 |
---|---|---|
committer | Michael Sevakis <jethead71@rockbox.org> | 2008-02-05 04:43:19 +0000 |
commit | 1f021af60cd0351a309666c2e32b3d1b8b2cbd6f (patch) | |
tree | 88710bcc59d80831327b00d59af0eb6a6f758de6 /firmware/target/arm/imx31/crt0.S | |
parent | 3f85a4bc97fb2120870fcd4a6650fd72d4a6338f (diff) | |
download | rockbox-1f021af60cd0351a309666c2e32b3d1b8b2cbd6f.tar.gz rockbox-1f021af60cd0351a309666c2e32b3d1b8b2cbd6f.zip |
Gigabeat S mixer: Make some progress. Get the tick and core sleep working using the AVIC. Redo the startup code to remap from IRAM and not include the lcd driver frambuffer in the remapping (until it can be moved). Clean up LCD driver. For other misc. changes, see the diffs. Now it progresses to ATA init and fails with -11 but without crashing or hanging. Replace all bootloaders.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16216 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/crt0.S')
-rw-r--r-- | firmware/target/arm/imx31/crt0.S | 422 |
1 files changed, 176 insertions, 246 deletions
diff --git a/firmware/target/arm/imx31/crt0.S b/firmware/target/arm/imx31/crt0.S index 2be2510bbd..9d50888536 100644 --- a/firmware/target/arm/imx31/crt0.S +++ b/firmware/target/arm/imx31/crt0.S | |||
@@ -24,7 +24,7 @@ | |||
24 | .global start | 24 | .global start |
25 | start: | 25 | start: |
26 | b newstart | 26 | b newstart |
27 | .space 4*16 | 27 | .space 4*12 /* Space for low vectors */ |
28 | 28 | ||
29 | 29 | ||
30 | /* Arm bootloader and startup code based on startup.s from the iPodLinux loader | 30 | /* Arm bootloader and startup code based on startup.s from the iPodLinux loader |
@@ -35,86 +35,53 @@ start: | |||
35 | */ | 35 | */ |
36 | 36 | ||
37 | newstart: | 37 | newstart: |
38 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ */ | 38 | msr cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ |
39 | 39 | ||
40 | #if !defined(BOOTLOADER) | 40 | #ifdef BOOTLOADER |
41 | #if !defined(DEBUG) | 41 | ldr r2, =remap_start |
42 | /* Copy exception handler code to address 0 */ | 42 | ldr r3, =remap_end |
43 | ldr r2, =_vectorsstart | 43 | ldr r5, =TTB_BASE_ADDR /* TTB pointer */ |
44 | ldr r3, =_vectorsend | 44 | ldr r6, =IRAM_BASE_ADDR |
45 | ldr r4, =_vectorscopy | 45 | mov r1, r6 |
46 | 1: | 46 | |
47 | cmp r3, r2 | 47 | 1: |
48 | ldrhi r5, [r4], #4 | 48 | cmp r3, r2 |
49 | strhi r5, [r2], #4 | 49 | ldrhi r4, [r2], #4 |
50 | bhi 1b | 50 | strhi r4, [r1], #4 |
51 | #else | 51 | bhi 1b |
52 | ldr r1, =vectors | 52 | |
53 | ldr r0, =irq_handler | 53 | mov pc, r6 |
54 | str r0, [r1, #24] | ||
55 | ldr r0, =fiq_handler | ||
56 | str r0, [r1, #28] | ||
57 | #endif | ||
58 | |||
59 | /* Zero out IBSS */ | ||
60 | ldr r2, =_iedata | ||
61 | ldr r3, =_iend | ||
62 | mov r4, #0 | ||
63 | 1: | ||
64 | cmp r3, r2 | ||
65 | strhi r4, [r2], #4 | ||
66 | bhi 1b | ||
67 | |||
68 | /* Copy the IRAM */ | ||
69 | ldr r2, =_iramcopy | ||
70 | ldr r3, =_iramstart | ||
71 | ldr r4, =_iramend | ||
72 | 1: | ||
73 | cmp r4, r3 | ||
74 | ldrhi r5, [r2], #4 | ||
75 | strhi r5, [r3], #4 | ||
76 | bhi 1b | ||
77 | #endif /* !BOOTLOADER */ | ||
78 | |||
79 | /* Initialise bss section to zero */ | ||
80 | ldr r2, =_edata | ||
81 | ldr r3, =_end | ||
82 | mov r4, #0 | ||
83 | 1: | ||
84 | cmp r3, r2 | ||
85 | strhi r4, [r2], #4 | ||
86 | bhi 1b | ||
87 | 54 | ||
88 | /* Set up some stack and munge it with 0xdeadbeef */ | 55 | remap_start: |
89 | ldr sp, =stackend | 56 | mrc p15, 0, r3, c1, c0, 0 /* perform writeback if D cache is enabled */ |
90 | mov r3, sp | 57 | tst r3, #(1 << 2) |
91 | ldr r2, =stackbegin | 58 | tsteq r3, #(1 << 12) |
92 | ldr r4, =0xdeadbeef | 59 | mcrne p15, 0, r0, c7, c10, 0 /* clean dcache */ |
93 | 1: | 60 | mov r0, #0 |
94 | cmp r3, r2 | 61 | mcrne p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ |
95 | strhi r4, [r2], #4 | 62 | mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ |
96 | bhi 1b | 63 | mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */ |
97 | 64 | ||
98 | #ifdef BOOTLOADER | 65 | mcr p15, 0, r0, c13, c0, 0 |
99 | /* Code for ARM bootloader targets other than iPod go here */ | 66 | mcr p15, 0, r0, c13, c0, 1 |
100 | |||
101 | mov r0, #0 | ||
102 | mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ | ||
103 | mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ | ||
104 | mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ | ||
105 | 67 | ||
106 | /* Also setup the Peripheral Port Remap register inside the core */ | 68 | /* Also setup the Peripheral Port Remap register inside the core */ |
107 | ldr r0, =0x40000015 /* start from AIPS 2GB region */ | 69 | mov r0, #0x40000000 /* start from AIPS 2GB region */ |
108 | mcr p15, 0, r0, c15, c2, 4 | 70 | add r0, r0, #0x15 |
71 | mcr p15, 0, r0, c15, c2, 4 | ||
109 | 72 | ||
110 | /*** L2 Cache setup/invalidation/disable ***/ | 73 | /*** L2 Cache setup/invalidation/disable ***/ |
111 | /* Disable L2 cache first */ | 74 | /* Disable L2 cache first */ |
112 | ldr r0, =L2CC_BASE_ADDR | 75 | mov r0, #L2CC_BASE_ADDR |
113 | ldr r2, [r0, #L2_CACHE_CTL_REG] | 76 | mov r1, #0 |
114 | bic r2, r2, #0x1 | 77 | str r1, [r0, #L2_CACHE_CTL_REG] |
115 | str r2, [r0, #L2_CACHE_CTL_REG] | 78 | |
116 | 79 | /* Disble L1 caches and memory manager */ | |
117 | 80 | bic r3, r3, #(1 << 1) | |
81 | bic r3, r3, #(1 << 2) | ||
82 | bic r3, r3, #(1 << 12) | ||
83 | mcr p15, 0, r3, c1, c0, 0 | ||
84 | |||
118 | /* | 85 | /* |
119 | * Configure L2 Cache: | 86 | * Configure L2 Cache: |
120 | * - 128k size(16k way) | 87 | * - 128k size(16k way) |
@@ -122,42 +89,21 @@ newstart: | |||
122 | * - 0 ws TAG/VALID/DIRTY | 89 | * - 0 ws TAG/VALID/DIRTY |
123 | * - 4 ws DATA R/W | 90 | * - 4 ws DATA R/W |
124 | */ | 91 | */ |
125 | ldr r1, [r0, #L2_CACHE_AUX_CTL_REG] | 92 | mov r1, #0x00130000 |
126 | and r1, r1, #0xFE000000 | 93 | orr r1, r1, #0x24 |
127 | ldr r2, =0x00030024 | 94 | str r1, [r0, #L2_CACHE_AUX_CTL_REG] |
128 | orr r1, r1, r2 | ||
129 | str r1, [r0, #L2_CACHE_AUX_CTL_REG] | ||
130 | 95 | ||
131 | /* Invalidate L2 */ | 96 | /* Invalidate L2 */ |
132 | ldr r1, =0x000000FF | 97 | mov r1, #0x000000FF |
133 | str r1, [r0, #L2_CACHE_INV_WAY_REG] | 98 | str r1, [r0, #L2_CACHE_INV_WAY_REG] |
134 | L2_loop: | 99 | L2_loop: |
135 | /* Poll Invalidate By Way register */ | 100 | /* Poll Invalidate By Way register */ |
136 | ldr r2, [r0, #L2_CACHE_INV_WAY_REG] | 101 | ldr r2, [r0, #L2_CACHE_INV_WAY_REG] |
137 | cmp r2, #0 | 102 | cmp r2, #0 |
138 | bne L2_loop | 103 | bne L2_loop |
104 | |||
139 | /*** End of L2 operations ***/ | 105 | /*** End of L2 operations ***/ |
140 | /* Set up stack for IRQ mode */ | ||
141 | mov r0,#0xd2 | ||
142 | msr cpsr, r0 | ||
143 | ldr sp, =irq_stack | ||
144 | /* Set up stack for FIQ mode */ | ||
145 | mov r0,#0xd1 | ||
146 | msr cpsr, r0 | ||
147 | ldr sp, =fiq_stack | ||
148 | 106 | ||
149 | /* Let abort and undefined modes use IRQ stack */ | ||
150 | mov r0,#0xd7 | ||
151 | msr cpsr, r0 | ||
152 | ldr sp, =irq_stack | ||
153 | mov r0,#0xdb | ||
154 | msr cpsr, r0 | ||
155 | ldr sp, =irq_stack | ||
156 | /* Switch to supervisor mode */ | ||
157 | mov r0,#0xd3 | ||
158 | msr cpsr, r0 | ||
159 | ldr sp, =stackend | ||
160 | |||
161 | /*remap memory as well as exception vectors*/ | 107 | /*remap memory as well as exception vectors*/ |
162 | /*for now this will be done in bootloader, especially | 108 | /*for now this will be done in bootloader, especially |
163 | if usb will be needed within the bootloader to load the | 109 | if usb will be needed within the bootloader to load the |
@@ -165,172 +111,155 @@ L2_loop: | |||
165 | (whether they be swi or irq)*/ | 111 | (whether they be swi or irq)*/ |
166 | 112 | ||
167 | /* TTB Initialisation */ | 113 | /* TTB Initialisation */ |
168 | ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) | 114 | mov r3, r5 |
169 | mov r1, #0 | 115 | add r2, r3, #TTB_SIZE |
170 | ldr r2, =(0x80000000+64*1024*1024) | 116 | mov r1, #0 |
171 | ttbloop: | 117 | ttbloop: |
172 | str r1, [r3], #4 | 118 | str r1, [r3], #4 |
173 | cmp r3, r2 | 119 | cmp r3, r2 |
174 | bne ttbloop | 120 | bne ttbloop |
175 | 121 | ||
176 | /* Set TTB base address */ | 122 | /* Set TTB base address */ |
177 | ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) | 123 | mov r3, r5 |
178 | mcr 15, 0 ,r3, cr2, cr0, 0 | 124 | mcr p15, 0, r3, c2, c0, 0 |
179 | /* Set all domains to manager status */ | 125 | /* Set all domains to manager status */ |
180 | mvn r3, #0 | 126 | mvn r3, #0 |
181 | mcr 15, 0, r3, cr3, cr0, 0 | 127 | mcr p15, 0, r3, c3, c0, 0 |
182 | 128 | ||
183 | /* Set page tables */ | 129 | /* Set page tables */ |
184 | 130 | ||
185 | /* Map each memory loc to itself, no cache */ | 131 | /* Map each memory loc to itself, no cache */ |
186 | mov r1, #0 /* Physical address */ | 132 | mov r1, #0 /* Physical address */ |
187 | ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) /* TTB pointer */ | 133 | mov r3, r5 |
188 | ldr r4, =(0x80000000+64*1024*1024-TTB_SIZE+0x4000) /* End position */ | 134 | add r4, r3, #TTB_SIZE /* End position */ |
189 | maploop1: | 135 | maploop1: |
190 | mov r2, r1 | 136 | mov r2, r1 |
191 | orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */ | 137 | orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */ |
192 | //orr r2, r2, #(0<<5) /* domain 0th */ | 138 | //orr r2, r2, #(0<<5) /* domain 0th */ |
193 | orr r2, r2, #(1<<4) /* should be "1" */ | 139 | orr r2, r2, #(1<<4) /* should be "1" */ |
194 | orr r2, r2, #(1<<1) /* Section signature */ | 140 | orr r2, r2, #(1<<1) /* Section signature */ |
195 | str r2, [r3], #4 | 141 | str r2, [r3], #4 |
196 | add r1, r1, #(1<<20) | 142 | add r1, r1, #(1<<20) |
197 | cmp r3, r4 | 143 | cmp r3, r4 |
198 | bne maploop1 | 144 | bne maploop1 |
199 | 145 | ||
200 | /* Map 0x80000000 -> 0x0, cached */ | 146 | /* Map 0x80000000 -> 0x0, cached */ |
201 | mov r1, #0x80000000 /* Physical address */ | 147 | mov r1, #0x80000000 /* Physical address */ |
202 | ldr r3, =(0x80000000+64*1024*1024-TTB_SIZE) /* TTB pointer */ | 148 | mov r3, r5 /* TTB pointer */ |
203 | ldr r4, =(0x80000000+64*1024*1024-TTB_SIZE+256) /* End position */ | 149 | add r4, r3, #64*4 /* End position */ |
204 | maploop2: | 150 | maploop2: |
205 | mov r2, r1 | 151 | mov r2, r1 |
206 | orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */ | 152 | orr r2, r2, #(1<<10) /* superuser - r/w, user - no access */ |
207 | //orr r2, r2, #(0<<5) /* domain 0th */ | 153 | //orr r2, r2, #(0<<5) /* domain 0th */ |
208 | orr r2, r2, #(1<<4) /* should be "1" */ | 154 | orr r2, r2, #(1<<4) /* should be "1" */ |
209 | orr r2, r2, #(1<<3) /* cache flags */ | 155 | orr r2, r2, #(1<<3) /* cache flags */ |
210 | orr r2, r2, #(1<<2) /* more cache stuff */ | 156 | orr r2, r2, #(1<<2) /* more cache stuff */ |
211 | orr r2, r2, #(1<<1) /* Section signature */ | 157 | orr r2, r2, #(1<<1) /* Section signature */ |
212 | str r2, [r3], #4 | 158 | str r2, [r3], #4 |
213 | add r1, r1, #(1<<20) | 159 | add r1, r1, #(1<<20) |
214 | cmp r3, r4 | 160 | bic r6, r1, #0xf0000000 |
215 | bne maploop2 | 161 | cmp r6, #0x00100000 /* Skip framebuffer */ |
162 | addeq r1, r1, #(1<<20) | ||
163 | cmp r3, r4 | ||
164 | bne maploop2 | ||
216 | 165 | ||
217 | /* Enable MMU */ | 166 | /* Enable MMU */ |
218 | mrc 15, 0, r3, cr1, cr0, 0 | 167 | |
219 | tst r3, #0x4 | 168 | mov r0, #0 |
220 | bleq clean_dcache | 169 | mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLB */ |
221 | tst r3, #0x1000 | 170 | mcr p15, 0, r0, c7, c7, 0 /* Invalidate icache and dcache */ |
222 | bleq clean_dcache | 171 | #if 1 |
223 | mov r0, #0 | 172 | mrc p15, 0, r0, c1, c0, 1 |
224 | 173 | bic r0, r0, #0x70 | |
225 | mcr 15, 0, r0, cr8, cr7, 0 /* Invalidate TLB */ | 174 | bic r0, r0, #0x07 |
226 | mcr 15, 0, r0, cr7, cr7, 0 /* Invalidate icache and dcache */ | 175 | mcr p15, 0, r0, c1, c0, 1 |
227 | mrc 15, 0, r0, cr1, cr0, 0 | 176 | #endif |
228 | orr r0, r0, #1 /* enable mmu bit */ | 177 | mrc p15, 0, r0, c1, c0, 0 |
229 | orr r0, r0, #(1<<2) /* enable dcache */ | 178 | orr r0, r0, #(1 << 0) /* enable mmu bit */ |
230 | orr r0, r0, #(1<<12) /* enable icache */ | 179 | orr r0, r0, #(1 << 2) /* enable dcache */ |
231 | mcr 15, 0, r0, cr1, cr0, 0 | 180 | bic r0, r0, #(1 << 11) /* no program flow prediction */ |
181 | orr r0, r0, #(1 << 12) /* enable icache */ | ||
182 | bic r0, r0, #(1 << 13) /* low vectors */ | ||
183 | orr r0, r0, #(1 << 14) /* Round-robin */ | ||
184 | bic r0, r0, #(1 << 21) /* No low latency interrupt */ | ||
185 | mcr p15, 0, r0, c1, c0, 0 | ||
232 | nop | 186 | nop |
233 | nop | 187 | nop |
234 | nop | 188 | nop |
235 | nop | 189 | nop |
190 | ldr pc, L_post_remap | ||
191 | L_post_remap: | ||
192 | .word remap_end | ||
193 | remap_end: | ||
236 | 194 | ||
237 | mov r0,#0 | 195 | #endif /* BOOTLOADER */ |
238 | ldr r1,=_vectorstart | ||
239 | mov r2,#0 | ||
240 | |||
241 | lp: ldr r3,[r1] | ||
242 | add r1,r1,#4 | ||
243 | str r3,[r0] | ||
244 | add r0,r0,#4 | ||
245 | add r2,r2,#1 | ||
246 | cmp r2,#16 | ||
247 | bne lp | ||
248 | bl main | ||
249 | |||
250 | .section .vectors,"aw" | ||
251 | _vectorstart: | ||
252 | ldr pc, [pc, #24] | ||
253 | ldr pc, [pc, #24] | ||
254 | ldr pc, [pc, #24] | ||
255 | ldr pc, [pc, #24] | ||
256 | ldr pc, [pc, #24] | ||
257 | ldr pc, [pc, #24] | ||
258 | ldr pc, [pc, #24] | ||
259 | ldr pc, [pc, #24] | ||
260 | |||
261 | /* Exception vectors */ | ||
262 | .global vectors | ||
263 | vectors: | ||
264 | .word start | ||
265 | .word undef_instr_handler | ||
266 | .word software_int_handler | ||
267 | .word prefetch_abort_handler | ||
268 | .word data_abort_handler | ||
269 | .word reserved_handler | ||
270 | .word irqz | ||
271 | .word fiqz | ||
272 | |||
273 | .text | ||
274 | .global irq | ||
275 | .global fiq | ||
276 | .global UIE | ||
277 | |||
278 | undef_instr_handler: | ||
279 | mov r0, lr | ||
280 | mov r1, #0 | ||
281 | b UIE | ||
282 | |||
283 | software_int_handler: | ||
284 | reserved_handler: | ||
285 | bl irq_handler | ||
286 | movs pc, lr | ||
287 | |||
288 | prefetch_abort_handler: | ||
289 | sub r0, lr, #4 | ||
290 | mov r1, #1 | ||
291 | b UIE | ||
292 | |||
293 | data_abort_handler: | ||
294 | sub r0, lr, #8 | ||
295 | mov r1, #2 | ||
296 | b UIE | ||
297 | |||
298 | /*not working....if we get here, let someone | ||
299 | know....*/ | ||
300 | irqz: bl irq_handler | ||
301 | fiqz: bl fiq_handler | ||
302 | |||
303 | UIE: | ||
304 | b UIE | ||
305 | 196 | ||
306 | /* 256 words of IRQ stack */ | 197 | #ifndef BOOTLOADER |
307 | .space 256*4 | 198 | /* Copy exception handler code to address 0 */ |
308 | irq_stack: | 199 | ldr r2, =_vectorsstart |
200 | ldr r3, =_vectorsend | ||
201 | ldr r4, =_vectorscopy | ||
202 | 1: | ||
203 | cmp r3, r2 | ||
204 | ldrhi r5, [r4], #4 | ||
205 | strhi r5, [r2], #4 | ||
206 | bhi 1b | ||
309 | 207 | ||
310 | /* 256 words of FIQ stack */ | 208 | /* Zero out IBSS */ |
311 | .space 256*4 | 209 | ldr r2, =_iedata |
312 | fiq_stack: | 210 | ldr r3, =_iend |
211 | mov r4, #0 | ||
212 | 1: | ||
213 | cmp r3, r2 | ||
214 | strhi r4, [r2], #4 | ||
215 | bhi 1b | ||
313 | 216 | ||
217 | /* Copy the IRAM */ | ||
218 | ldr r2, =_iramcopy | ||
219 | ldr r3, =_iramstart | ||
220 | ldr r4, =_iramend | ||
221 | 1: | ||
222 | cmp r4, r3 | ||
223 | ldrhi r5, [r2], #4 | ||
224 | strhi r5, [r3], #4 | ||
225 | bhi 1b | ||
226 | #endif /* BOOTLOADER */ | ||
314 | 227 | ||
315 | #else /* BOOTLOADER */ | 228 | /* Initialise bss section to zero */ |
229 | ldr r2, =_edata | ||
230 | ldr r3, =_end | ||
231 | mov r4, #0 | ||
232 | 1: | ||
233 | cmp r3, r2 | ||
234 | strhi r4, [r2], #4 | ||
235 | bhi 1b | ||
236 | |||
237 | /* Set up some stack and munge it with 0xdeadbeef */ | ||
238 | ldr sp, =stackend | ||
239 | ldr r2, =stackbegin | ||
240 | ldr r3, =0xdeadbeef | ||
241 | 1: | ||
242 | cmp sp, r2 | ||
243 | strhi r3, [r2], #4 | ||
244 | bhi 1b | ||
245 | |||
246 | /* Set up stack for IRQ mode */ | ||
247 | msr cpsr_c, #0xd2 | ||
248 | ldr sp, =irq_stack | ||
316 | 249 | ||
317 | /* Set up stack for IRQ mode */ | ||
318 | msr cpsr_c, #0xd2 | ||
319 | ldr sp, =irq_stack | ||
320 | /* Set up stack for FIQ mode */ | 250 | /* Set up stack for FIQ mode */ |
321 | msr cpsr_c, #0xd1 | 251 | msr cpsr_c, #0xd1 |
322 | ldr sp, =fiq_stack | 252 | ldr sp, =fiq_stack |
323 | 253 | ||
324 | /* Let abort and undefined modes use IRQ stack */ | 254 | /* Let abort and undefined modes use IRQ stack */ |
325 | msr cpsr_c, #0xd7 | 255 | msr cpsr_c, #0xd7 |
326 | ldr sp, =irq_stack | 256 | ldr sp, =irq_stack |
327 | msr cpsr_c, #0xdb | 257 | msr cpsr_c, #0xdb |
328 | ldr sp, =irq_stack | 258 | ldr sp, =irq_stack |
329 | /* Switch to supervisor mode */ | 259 | |
330 | msr cpsr_c, #0xd3 | 260 | /* Switch back to supervisor mode */ |
331 | ldr sp, =stackend | 261 | msr cpsr_c, #0xd3 |
332 | bl main | 262 | bl main |
333 | /* main() should never return */ | ||
334 | 263 | ||
335 | /* Exception handlers. Will be copied to address 0 after memory remapping */ | 264 | /* Exception handlers. Will be copied to address 0 after memory remapping */ |
336 | _vectorstart: | 265 | _vectorstart: |
@@ -358,8 +287,6 @@ vectors: | |||
358 | 287 | ||
359 | .text | 288 | .text |
360 | 289 | ||
361 | .global irq | ||
362 | .global fiq | ||
363 | .global UIE | 290 | .global UIE |
364 | 291 | ||
365 | /* All illegal exceptions call into UIE with exception address as first | 292 | /* All illegal exceptions call into UIE with exception address as first |
@@ -389,6 +316,11 @@ data_abort_handler: | |||
389 | mov r1, #2 | 316 | mov r1, #2 |
390 | b UIE | 317 | b UIE |
391 | 318 | ||
319 | #ifdef BOOTLOADER | ||
320 | UIE: | ||
321 | b UIE | ||
322 | #endif | ||
323 | |||
392 | /* 256 words of IRQ stack */ | 324 | /* 256 words of IRQ stack */ |
393 | .space 256*4 | 325 | .space 256*4 |
394 | irq_stack: | 326 | irq_stack: |
@@ -396,5 +328,3 @@ irq_stack: | |||
396 | /* 256 words of FIQ stack */ | 328 | /* 256 words of FIQ stack */ |
397 | .space 256*4 | 329 | .space 256*4 |
398 | fiq_stack: | 330 | fiq_stack: |
399 | |||
400 | #endif /* BOOTLOADER */ | ||