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author | Michael Sevakis <jethead71@rockbox.org> | 2010-04-23 15:32:50 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2010-04-23 15:32:50 +0000 |
commit | 11cca264ff57ad0b234bd1cd2c9a2366b967feb7 (patch) | |
tree | 7693e7150d5abc9687966cc248bfbd550d356964 /firmware/target/arm/imx31/ccm-imx31.c | |
parent | 6cee7579dbdc4d41c4df08c9395cf96c952ebab1 (diff) | |
download | rockbox-11cca264ff57ad0b234bd1cd2c9a2366b967feb7.tar.gz rockbox-11cca264ff57ad0b234bd1cd2c9a2366b967feb7.zip |
i.MX31/Gigabeat S: Implement frequency and voltage scaling-- 1.6V for 528MHz, and 1.35V for 264MHz and 132MHz. Keep DPTC overdrive ( > 400MHz) voltage scaling off for now because of uncertainties. Simplify the (working) mess later.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25699 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/ccm-imx31.c')
-rw-r--r-- | firmware/target/arm/imx31/ccm-imx31.c | 62 |
1 files changed, 47 insertions, 15 deletions
diff --git a/firmware/target/arm/imx31/ccm-imx31.c b/firmware/target/arm/imx31/ccm-imx31.c index 0d166e5dbf..2cf2080cf1 100644 --- a/firmware/target/arm/imx31/ccm-imx31.c +++ b/firmware/target/arm/imx31/ccm-imx31.c | |||
@@ -24,7 +24,8 @@ | |||
24 | #include "cpu.h" | 24 | #include "cpu.h" |
25 | #include "ccm-imx31.h" | 25 | #include "ccm-imx31.h" |
26 | 26 | ||
27 | unsigned int ccm_get_src_pll(void) | 27 | /* Return the current source pll for MCU */ |
28 | enum IMX31_PLLS ccm_get_src_pll(void) | ||
28 | { | 29 | { |
29 | return (CCM_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU; | 30 | return (CCM_PMCR0 & 0xC0000000) == 0 ? PLL_SERIAL : PLL_MCU; |
30 | } | 31 | } |
@@ -45,8 +46,21 @@ void ccm_module_clock_gating(enum IMX31_CG_LIST cg, enum IMX31_CG_MODES mode) | |||
45 | imx31_regmod32(reg, mode << shift, mask); | 46 | imx31_regmod32(reg, mode << shift, mask); |
46 | } | 47 | } |
47 | 48 | ||
49 | /* Decode PLL output frequency from register value */ | ||
50 | unsigned int ccm_calc_pll_rate(unsigned int infreq, unsigned long regval) | ||
51 | { | ||
52 | uint32_t mfn = regval & 0x3ff; | ||
53 | uint32_t pd = ((regval >> 26) & 0xf) + 1; | ||
54 | uint32_t mfd = ((regval >> 16) & 0x3ff) + 1; | ||
55 | uint32_t mfi = (regval >> 10) & 0xf; | ||
56 | |||
57 | mfi = mfi <= 5 ? 5 : mfi; | ||
58 | |||
59 | return 2ull*infreq*(mfi * mfd + mfn) / (mfd * pd); | ||
60 | } | ||
61 | |||
48 | /* Get the PLL reference clock frequency in HZ */ | 62 | /* Get the PLL reference clock frequency in HZ */ |
49 | unsigned int ccm_get_pll_ref_clk(void) | 63 | unsigned int ccm_get_pll_ref_clk_rate(void) |
50 | { | 64 | { |
51 | if ((CCM_CCMR & (3 << 1)) == (1 << 1)) | 65 | if ((CCM_CCMR & (3 << 1)) == (1 << 1)) |
52 | return CONFIG_CKIL_FREQ * 1024; | 66 | return CONFIG_CKIL_FREQ * 1024; |
@@ -55,41 +69,59 @@ unsigned int ccm_get_pll_ref_clk(void) | |||
55 | } | 69 | } |
56 | 70 | ||
57 | /* Return PLL frequency in HZ */ | 71 | /* Return PLL frequency in HZ */ |
58 | unsigned int ccm_get_pll(enum IMX31_PLLS pll) | 72 | unsigned int ccm_get_pll_rate(enum IMX31_PLLS pll) |
59 | { | 73 | { |
60 | uint32_t infreq = ccm_get_pll_ref_clk(); | 74 | return ccm_calc_pll_rate(ccm_get_pll_ref_clk_rate(), (&CCM_MPCTL)[pll]); |
61 | uint32_t reg = (&CCM_MPCTL)[pll]; | 75 | } |
62 | uint32_t mfn = reg & 0x3ff; | ||
63 | uint32_t pd = ((reg >> 26) & 0xf) + 1; | ||
64 | uint64_t mfd = ((reg >> 16) & 0x3ff) + 1; | ||
65 | uint32_t mfi = (reg >> 10) & 0xf; | ||
66 | 76 | ||
67 | mfi = mfi <= 5 ? 5 : mfi; | 77 | unsigned int ccm_get_mcu_clk(void) |
78 | { | ||
79 | unsigned int pllnum = ccm_get_src_pll(); | ||
80 | unsigned int fpll = ccm_get_pll_rate(pllnum); | ||
81 | unsigned int mcu_podf = (CCM_PDR0 & 0x7) + 1; | ||
68 | 82 | ||
69 | return 2*infreq*(mfi * mfd + mfn) / (mfd * pd); | 83 | return fpll / mcu_podf; |
70 | } | 84 | } |
71 | 85 | ||
72 | unsigned int ccm_get_ipg_clk(void) | 86 | unsigned int ccm_get_ipg_clk(void) |
73 | { | 87 | { |
74 | unsigned int pllnum = ccm_get_src_pll(); | 88 | unsigned int pllnum = ccm_get_src_pll(); |
75 | unsigned int pll = ccm_get_pll(pllnum); | 89 | unsigned int fpll = ccm_get_pll_rate(pllnum); |
76 | uint32_t reg = CCM_PDR0; | 90 | uint32_t reg = CCM_PDR0; |
77 | unsigned int max_pdf = ((reg >> 3) & 0x7) + 1; | 91 | unsigned int max_pdf = ((reg >> 3) & 0x7) + 1; |
78 | unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1; | 92 | unsigned int ipg_pdf = ((reg >> 6) & 0x3) + 1; |
79 | 93 | ||
80 | return pll / (max_pdf * ipg_pdf); | 94 | return fpll / (max_pdf * ipg_pdf); |
81 | } | 95 | } |
82 | 96 | ||
83 | unsigned int ccm_get_ahb_clk(void) | 97 | unsigned int ccm_get_ahb_clk(void) |
84 | { | 98 | { |
85 | unsigned int pllnum = ccm_get_src_pll(); | 99 | unsigned int pllnum = ccm_get_src_pll(); |
86 | unsigned int pll = ccm_get_pll(pllnum); | 100 | unsigned int fpll = ccm_get_pll_rate(pllnum); |
87 | unsigned int max_pdf = ((CCM_PDR0 >> 3) & 0x7) + 1; | 101 | unsigned int max_pdf = ((CCM_PDR0 >> 3) & 0x7) + 1; |
88 | 102 | ||
89 | return pll / max_pdf; | 103 | return fpll / max_pdf; |
90 | } | 104 | } |
91 | 105 | ||
92 | unsigned int ccm_get_ata_clk(void) | 106 | unsigned int ccm_get_ata_clk(void) |
93 | { | 107 | { |
94 | return ccm_get_ipg_clk(); | 108 | return ccm_get_ipg_clk(); |
95 | } | 109 | } |
110 | |||
111 | /* Write new values to the current PLL and post-dividers */ | ||
112 | void ccm_set_mcupll_and_pdr(unsigned long pllctl, unsigned long pdr) | ||
113 | { | ||
114 | unsigned int pll = ccm_get_src_pll(); | ||
115 | volatile unsigned long *pllreg = &(&CCM_MPCTL)[pll]; | ||
116 | unsigned long fref = ccm_get_pll_ref_clk_rate(); | ||
117 | unsigned long curfreq = ccm_calc_pll_rate(fref, *pllreg); | ||
118 | unsigned long newfreq = ccm_calc_pll_rate(fref, pllctl); | ||
119 | |||
120 | if (newfreq > curfreq) | ||
121 | CCM_PDR0 = pdr; | ||
122 | |||
123 | *pllreg = pllctl; | ||
124 | |||
125 | if (newfreq <= curfreq) | ||
126 | CCM_PDR0 = pdr; | ||
127 | } | ||