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author | Michael Sevakis <jethead71@rockbox.org> | 2010-04-23 15:32:50 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2010-04-23 15:32:50 +0000 |
commit | 11cca264ff57ad0b234bd1cd2c9a2366b967feb7 (patch) | |
tree | 7693e7150d5abc9687966cc248bfbd550d356964 /firmware/target/arm/imx31/avic-imx31.h | |
parent | 6cee7579dbdc4d41c4df08c9395cf96c952ebab1 (diff) | |
download | rockbox-11cca264ff57ad0b234bd1cd2c9a2366b967feb7.tar.gz rockbox-11cca264ff57ad0b234bd1cd2c9a2366b967feb7.zip |
i.MX31/Gigabeat S: Implement frequency and voltage scaling-- 1.6V for 528MHz, and 1.35V for 264MHz and 132MHz. Keep DPTC overdrive ( > 400MHz) voltage scaling off for now because of uncertainties. Simplify the (working) mess later.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25699 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/avic-imx31.h')
-rw-r--r-- | firmware/target/arm/imx31/avic-imx31.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/firmware/target/arm/imx31/avic-imx31.h b/firmware/target/arm/imx31/avic-imx31.h index a049713600..ba8f91cc1a 100644 --- a/firmware/target/arm/imx31/avic-imx31.h +++ b/firmware/target/arm/imx31/avic-imx31.h | |||
@@ -172,7 +172,11 @@ struct avic_map | |||
172 | }; | 172 | }; |
173 | }; | 173 | }; |
174 | 174 | ||
175 | /* #define IRQ priorities for different modules (0-15) */ | ||
175 | #define INT_PRIO_DEFAULT 7 | 176 | #define INT_PRIO_DEFAULT 7 |
177 | #define INT_PRIO_DVFS (INT_PRIO_DEFAULT+1) | ||
178 | #define INT_PRIO_DPTC (INT_PRIO_DEFAULT+1) | ||
179 | #define INT_PRIO_SDMA (INT_PRIO_DEFAULT+2) | ||
176 | 180 | ||
177 | enum INT_TYPE | 181 | enum INT_TYPE |
178 | { | 182 | { |
@@ -210,4 +214,37 @@ void avic_set_int_priority(enum IMX31_INT_LIST ints, | |||
210 | void avic_disable_int(enum IMX31_INT_LIST ints); | 214 | void avic_disable_int(enum IMX31_INT_LIST ints); |
211 | void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype); | 215 | void avic_set_int_type(enum IMX31_INT_LIST ints, enum INT_TYPE intstype); |
212 | 216 | ||
217 | #define AVIC_NIL_DISABLE 0xf | ||
218 | #define AVIC_NIL_ENABLE 0x1f | ||
219 | void avic_set_ni_level(unsigned int level); | ||
220 | |||
221 | /* Call a service routine while allowing preemption by interrupts of higher | ||
222 | * priority. r4-r7 must be preserved for epilogue code to restore context. */ | ||
223 | #define AVIC_NESTED_NI_CALL_PROLOGUE() \ | ||
224 | ({ asm volatile ( \ | ||
225 | "sub lr, lr, #4 \n" /* prepare return address */ \ | ||
226 | "stmfd sp!, { r0-r7, r12, lr } \n" /* preserve return context */ \ | ||
227 | "mov r0, #0x68000000 \n" /* AVIC_BASE_ADDR */ \ | ||
228 | "mrs r4, spsr \n" /* save SPSR_irq */ \ | ||
229 | "ldr r5, [r0, #0x04] \n" /* save NIMASK */ \ | ||
230 | "ldr r1, [r0, #0x40] \n" /* load NIVECSR */ \ | ||
231 | "mov r2, sp \n" /* remember IRQ stack to use in call */ \ | ||
232 | "str r1, [r0, #0x04] \n" /* copy NIVECSR to NIMASK */ \ | ||
233 | "cps #0x13 \n" /* switch to SVC mode (+ unmask IRQ) */ \ | ||
234 | "mov r6, sp \n" /* save SP_svc */ \ | ||
235 | "mov r7, lr \n" /* save LR_svc */ \ | ||
236 | "mov sp, r2 \n" /* switch to SP_irq */ \ | ||
237 | ); }) | ||
238 | |||
239 | #define AVIC_NESTED_NI_CALL_EPILOGUE() \ | ||
240 | ({ asm volatile ( \ | ||
241 | "mov sp, r6 \n" /* restore SP_svc */ \ | ||
242 | "mov lr, r7 \n" /* restore LR_svc */ \ | ||
243 | "cps #0x12 \n" /* return to IRQ mode (+ mask IRQ) */ \ | ||
244 | "mov r0, #0x68000000 \n" /* AVIC BASE ADDR */ \ | ||
245 | "msr spsr_cxsf, r4 \n" /* restore SPSR_irq */ \ | ||
246 | "str r5, [r0, #0x04] \n" /* restore NIMASK */ \ | ||
247 | "ldmfd sp!, { r0-r7, r12, pc }^ \n" /* reload context and return */ \ | ||
248 | ); }) | ||
249 | |||
213 | #endif /* AVIC_IMX31_H */ | 250 | #endif /* AVIC_IMX31_H */ |