imx233: implement emi frequency scaling (disabled by default)

CPU frequency scaling is basically useless without scaling the
memory frequency. On the i.MX233, the EMI (external memory
interface) and DRAM blocks are responsable for the DDR settings.
This commits implements emi frequency scaling. Only some settings
are implemented and the timings values only apply to mDDR
(extracted from Sigmatel linux port) and have been checked to
work on the Fuze+ and Zen X-Fi2/3. This feature is still disabled
by default but I expected some battery life savings by boosting
higher to 454MHz and unboosting lower to 64MHz.
Note that changing the emi frequency is particularly tricky and
to avoid writing it entirely in assembly we rely on the compiler
to not use the stack except in the prolog and epilog (because
it's in dram which is disabled when doing the change) and to put
constant pools in iram which should always be true if the
compiler isn't completely dumb and since the code itself is put
in iram. If this proves to be insufficient, one can always switch
the stack to the irq stack since interrupts are disabled during
the change.

Change-Id: If6ef5357f7ff091130ca1063e48536c6028f23ba

1 files changed, 21 insertions, 9 deletions

diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h
index 5515597570..c6073a9ae3 100644
--- a/firmware/target/arm/imx233/system-target.h
+++ b/firmware/target/arm/imx233/system-target.h
@@ -37,6 +37,18 @@
 
 #define HW_DIGCTL_MICROSECONDS  (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0xC0))
 
+#define HW_DIGCTL_ARMCACHE      (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0x2b0))
+#define HW_DIGCTL_ARMCACHE__ITAG_SS_BP  0
+#define HW_DIGCTL_ARMCACHE__ITAG_SS_BM  (3 << 0)
+#define HW_DIGCTL_ARMCACHE__DTAG_SS_BP  4
+#define HW_DIGCTL_ARMCACHE__DTAG_SS_BM  (3 << 4)
+#define HW_DIGCTL_ARMCACHE__CACHE_SS_BP  8
+#define HW_DIGCTL_ARMCACHE__CACHE_SS_BM  (3 << 8)
+#define HW_DIGCTL_ARMCACHE__DRTY_SS_BP  12
+#define HW_DIGCTL_ARMCACHE__DRTY_SS_BM  (3 << 12)
+#define HW_DIGCTL_ARMCACHE__VALID_SS_BP  16
+#define HW_DIGCTL_ARMCACHE__VALID_SS_BM  (3 << 16)
+
 /* USB Phy */
 #define HW_USBPHY_BASE          0x8007C000 
 #define HW_USBPHY_PWD           (*(volatile uint32_t *)(HW_USBPHY_BASE + 0))
@@ -48,17 +60,17 @@
  * Absolute maximum CPU speed: 454.74 MHz
  * Intermediate CPU speeds: 392.73 MHz, 360MHz, 261.82 MHz, 64 MHz
  * Absolute minimum CPU speed: 24 MHz */
-#define IMX233_CPUFREQ_454_MHz  454740000
-#define IMX233_CPUFREQ_392_MHz  392730000
-#define IMX233_CPUFREQ_360_MHz  360000000
-#define IMX233_CPUFREQ_261_MHz  261820000
-#define IMX233_CPUFREQ_64_MHz    64000000
-#define IMX233_CPUFREQ_24_MHz    24000000
+#define IMX233_CPUFREQ_454_MHz  454740
+#define IMX233_CPUFREQ_392_MHz  392730
+#define IMX233_CPUFREQ_360_MHz  360000
+#define IMX233_CPUFREQ_261_MHz  261820
+#define IMX233_CPUFREQ_64_MHz    64000
+#define IMX233_CPUFREQ_24_MHz    24000
 
-#define CPUFREQ_DEFAULT     IMX233_CPUFREQ_261_MHz
-#define CPUFREQ_NORMAL      IMX233_CPUFREQ_261_MHz
+#define CPUFREQ_DEFAULT     IMX233_CPUFREQ_64_MHz
+#define CPUFREQ_NORMAL      IMX233_CPUFREQ_64_MHz
 #define CPUFREQ_MAX         IMX233_CPUFREQ_454_MHz
-#define CPUFREQ_SLEEP       IMX233_CPUFREQ_261_MHz
+#define CPUFREQ_SLEEP       IMX233_CPUFREQ_64_MHz
 
 void udelay(unsigned us);
 bool imx233_us_elapsed(uint32_t ref, unsigned us_delay);