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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-16 17:21:12 +0200 |
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committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-16 18:21:48 +0200 |
commit | 2d12ef6c736699dfef5b97d693225e9a4892bde8 (patch) | |
tree | 7c65e1176c759c0344d5a14525475a8f9b72a5af /firmware/target/arm/imx233/rtc-imx233.h | |
parent | 3e8c2dc46d843575096e92bd82886c7d6d44855d (diff) | |
download | rockbox-2d12ef6c736699dfef5b97d693225e9a4892bde8.tar.gz rockbox-2d12ef6c736699dfef5b97d693225e9a4892bde8.zip |
imx233: rewrite rtc using new registers
Change-Id: I30794dac2175d5717ea8e05e911abec65a214c44
Diffstat (limited to 'firmware/target/arm/imx233/rtc-imx233.h')
-rw-r--r-- | firmware/target/arm/imx233/rtc-imx233.h | 65 |
1 files changed, 7 insertions, 58 deletions
diff --git a/firmware/target/arm/imx233/rtc-imx233.h b/firmware/target/arm/imx233/rtc-imx233.h index baf30df7c5..3ad523bdbe 100644 --- a/firmware/target/arm/imx233/rtc-imx233.h +++ b/firmware/target/arm/imx233/rtc-imx233.h | |||
@@ -25,60 +25,9 @@ | |||
25 | #include "system.h" | 25 | #include "system.h" |
26 | #include "cpu.h" | 26 | #include "cpu.h" |
27 | 27 | ||
28 | #define HW_RTC_BASE 0x8005c000 | 28 | #include "regs/regs-rtc.h" |
29 | 29 | ||
30 | #define HW_RTC_CTRL (*(volatile uint32_t *)(HW_RTC_BASE + 0x0)) | 30 | #define HW_RTC_PERSISTENTn(n) *(&HW_RTC_PERSISTENT0 + 4 * (n)) |
31 | #define HW_RTC_CTRL__ALARM_IRQ_EN (1 << 0) | ||
32 | #define HW_RTC_CTRL__ONEMSEC_IRQ_EN (1 << 1) | ||
33 | #define HW_RTC_CTRL__ALARM_IRQ (1 << 2) | ||
34 | #define HW_RTC_CTRL__ONEMSEC_IRQ (1 << 3) | ||
35 | #define HW_RTC_CTRL__WATCHDOGEN (1 << 4) | ||
36 | #define HW_RTC_CTRL__FORCE_UPDATE (1 << 5) | ||
37 | #define HW_RTC_CTRL__SUPPRESS_COPY2ANALOG (1 << 6) | ||
38 | |||
39 | #define HW_RTC_STAT (*(volatile uint32_t *)(HW_RTC_BASE + 0x10)) | ||
40 | #define HW_RTC_STAT__NEW_REGS_BP 8 | ||
41 | #define HW_RTC_STAT__NEW_REGS_BM 0xff00 | ||
42 | #define HW_RTC_STAT__STALE_REGS_BP 16 | ||
43 | #define HW_RTC_STAT__STALE_REGS_BM 0xff0000 | ||
44 | #define HW_RTC_STAT__XTAL32768_PRESENT (1 << 27) | ||
45 | #define HW_RTC_STAT__XTAL32000_PRESENT (1 << 28) | ||
46 | #define HW_RTC_STAT__WATCHDOG_PRESENT (1 << 29) | ||
47 | #define HW_RTC_STAT__ALARM_PRESENT (1 << 30) | ||
48 | #define HW_RTC_STAT__RTC_PRESENT (1 << 31) | ||
49 | |||
50 | #define HW_RTC_MILLISECONDS (*(volatile uint32_t *)(HW_RTC_BASE + 0x20)) | ||
51 | |||
52 | #define HW_RTC_SECONDS (*(volatile uint32_t *)(HW_RTC_BASE + 0x30)) | ||
53 | |||
54 | #define HW_RTC_ALARM (*(volatile uint32_t *)(HW_RTC_BASE + 0x40)) | ||
55 | |||
56 | #define HW_RTC_WATCHDOG (*(volatile uint32_t *)(HW_RTC_BASE + 0x50)) | ||
57 | |||
58 | #define HW_RTC_PERSISTENTx(x) (*(volatile uint32_t *)(HW_RTC_BASE + 0x60 + (x) * 0x10)) | ||
59 | |||
60 | #define HW_RTC_PERSISTENT0 (*(volatile uint32_t *)(HW_RTC_BASE + 0x60)) | ||
61 | #define HW_RTC_PERSISTENT0__CLOCKSOURCE (1 << 0) | ||
62 | #define HW_RTC_PERSISTENT0__ALARM_WAKE_EN (1 << 1) | ||
63 | #define HW_RTC_PERSISTENT0__ALARM_EN (1 << 2) | ||
64 | #define HW_RTC_PERSISTENT0__XTAL24MHZ_PWRUP (1 << 4) | ||
65 | #define HW_RTC_PERSISTENT0__XTAL32KHZ_PWRUP (1 << 5) | ||
66 | #define HW_RTC_PERSISTENT0__XTAL32_FREQ (1 << 6) | ||
67 | #define HW_RTC_PERSISTENT0__ALARM_WAKE (1 << 7) | ||
68 | #define HW_RTC_PERSISTENT0__AUTO_RESTART (1 << 17) | ||
69 | #define HW_RTC_PERSISTENT0__SPARE_BP 18 | ||
70 | #define HW_RTC_PERSISTENT0__SPARE_BM (0x3fff << 18) | ||
71 | #define HW_RTC_PERSISTENT0__SPARE__RELEASE_GND (1 << 19) | ||
72 | |||
73 | #define HW_RTC_PERSISTENT1 (*(volatile uint32_t *)(HW_RTC_BASE + 0x70)) | ||
74 | |||
75 | #define HW_RTC_PERSISTENT2 (*(volatile uint32_t *)(HW_RTC_BASE + 0x80)) | ||
76 | |||
77 | #define HW_RTC_PERSISTENT3 (*(volatile uint32_t *)(HW_RTC_BASE + 0x90)) | ||
78 | |||
79 | #define HW_RTC_PERSISTENT4 (*(volatile uint32_t *)(HW_RTC_BASE + 0xa0)) | ||
80 | |||
81 | #define HW_RTC_PERSISTENT5 (*(volatile uint32_t *)(HW_RTC_BASE + 0xb0)) | ||
82 | 31 | ||
83 | struct imx233_rtc_info_t | 32 | struct imx233_rtc_info_t |
84 | { | 33 | { |
@@ -88,7 +37,7 @@ struct imx233_rtc_info_t | |||
88 | 37 | ||
89 | static inline void imx233_rtc_init(void) | 38 | static inline void imx233_rtc_init(void) |
90 | { | 39 | { |
91 | __REG_CLR(HW_RTC_CTRL) = __BLOCK_CLKGATE; | 40 | BF_CLR(RTC_CTRL, CLKGATE); |
92 | } | 41 | } |
93 | 42 | ||
94 | static inline uint32_t imx233_rtc_read_seconds(void) | 43 | static inline uint32_t imx233_rtc_read_seconds(void) |
@@ -98,21 +47,21 @@ static inline uint32_t imx233_rtc_read_seconds(void) | |||
98 | 47 | ||
99 | static inline uint32_t imx233_rtc_read_persistent(int idx) | 48 | static inline uint32_t imx233_rtc_read_persistent(int idx) |
100 | { | 49 | { |
101 | return HW_RTC_PERSISTENTx(idx); | 50 | return HW_RTC_PERSISTENTn(idx); |
102 | } | 51 | } |
103 | 52 | ||
104 | static inline void imx233_rtc_clear_msec_irq(void) | 53 | static inline void imx233_rtc_clear_msec_irq(void) |
105 | { | 54 | { |
106 | __REG_CLR(HW_RTC_CTRL) = HW_RTC_CTRL__ONEMSEC_IRQ; | 55 | BF_CLR(RTC_CTRL, ONEMSEC_IRQ); |
107 | } | 56 | } |
108 | 57 | ||
109 | static inline void imx233_rtc_enable_msec_irq(bool enable) | 58 | static inline void imx233_rtc_enable_msec_irq(bool enable) |
110 | { | 59 | { |
111 | imx233_rtc_clear_msec_irq(); | 60 | imx233_rtc_clear_msec_irq(); |
112 | if(enable) | 61 | if(enable) |
113 | __REG_SET(HW_RTC_CTRL) = HW_RTC_CTRL__ONEMSEC_IRQ_EN; | 62 | BF_SET(RTC_CTRL, ONEMSEC_IRQ_EN); |
114 | else | 63 | else |
115 | __REG_CLR(HW_RTC_CTRL) = HW_RTC_CTRL__ONEMSEC_IRQ_EN; | 64 | BF_CLR(RTC_CTRL, ONEMSEC_IRQ_EN); |
116 | } | 65 | } |
117 | 66 | ||
118 | void imx233_rtc_write_seconds(uint32_t seconds); | 67 | void imx233_rtc_write_seconds(uint32_t seconds); |