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author | Amaury Pouly <amaury.pouly@gmail.com> | 2012-05-19 13:31:50 +0200 |
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committer | Amaury Pouly <amaury.pouly@gmail.com> | 2012-05-19 16:10:52 +0200 |
commit | 61b129ac1e41014fc5da846c48a361c7ec752d76 (patch) | |
tree | 4c2440ac4c14a29dcef055c73eae149f1aa58848 /firmware/target/arm/imx233/gpmi-imx233.h | |
parent | bbbfd9f3d389a2d6f9049802ddd5f9b11870bc7a (diff) | |
download | rockbox-61b129ac1e41014fc5da846c48a361c7ec752d76.tar.gz rockbox-61b129ac1e41014fc5da846c48a361c7ec752d76.zip |
imx233: add gpmi stubs
Change-Id: I5ddcf392e6ffc27513170b1ee768c96cdc5a83d4
Diffstat (limited to 'firmware/target/arm/imx233/gpmi-imx233.h')
-rw-r--r-- | firmware/target/arm/imx233/gpmi-imx233.h | 197 |
1 files changed, 197 insertions, 0 deletions
diff --git a/firmware/target/arm/imx233/gpmi-imx233.h b/firmware/target/arm/imx233/gpmi-imx233.h new file mode 100644 index 0000000000..5850cbd92a --- /dev/null +++ b/firmware/target/arm/imx233/gpmi-imx233.h | |||
@@ -0,0 +1,197 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2011 by Amaury Pouly | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef __GPMI_IMX233_H__ | ||
22 | #define __GPMI_IMX233_H__ | ||
23 | |||
24 | #include "system.h" | ||
25 | |||
26 | /* GPMI */ | ||
27 | |||
28 | #define HW_GPMI_BASE 0x8000c000 | ||
29 | |||
30 | #define HW_GPMI_CTRL0 (*(volatile uint32_t *)(HW_GPMI_BASE + 0x0)) | ||
31 | #define HW_GPMI_CTRL0__XFER_COUNT_BP 0 | ||
32 | #define HW_GPMI_CTRL0__XFER_COUNT_BM 0xffff | ||
33 | #define HW_GPMI_CTRL0__ADDRESS_INCREMENT (1 << 16) | ||
34 | #define HW_GPMI_CTRL0__CS_BP 20 | ||
35 | #define HW_GPMI_CTRL0__CS_BM (0x3 << 20) | ||
36 | #define HW_GPMI_CTRL0__LOCK_CS (1 << 22) | ||
37 | #define HW_GPMI_CTRL0__WORD_LENGTH (1 << 23) | ||
38 | #define HW_GPMI_CTRL0__WORD_LENGTH__16_BIT (0 << 23) | ||
39 | #define HW_GPMI_CTRL0__WORD_LENGTH__8_BIT (1 << 23) | ||
40 | #define HW_GPMI_CTRL0__COMMAND_MODE_BP 24 | ||
41 | #define HW_GPMI_CTRL0__COMMAND_MODE_BM (0x3 << 24) | ||
42 | #define HW_GPMI_CTRL0__COMMAND_MODE__WRITE (0 << 24) | ||
43 | #define HW_GPMI_CTRL0__COMMAND_MODE__READ (1 << 24) | ||
44 | #define HW_GPMI_CTRL0__COMMAND_MODE__READ_AND_COMPARE (2 << 24) | ||
45 | #define HW_GPMI_CTRL0__COMMAND_MODE__WAIT_FOR_READY (3 << 24) | ||
46 | #define HW_GPMI_CTRL0__TIMEOUT_IRQ_EN (1 << 27) | ||
47 | #define HW_GPMI_CTRL0__RUN (1 << 29) | ||
48 | |||
49 | #define HW_GPMI_COMPARE (*(volatile uint32_t *)(HW_GPMI_BASE + 0x10)) | ||
50 | #define HW_GPMI_COMPARE__REFERENCE_BP 0 | ||
51 | #define HW_GPMI_COMPARE__REFERENCE_BM 0xffff | ||
52 | #define HW_GPMI_COMPARE__MASK_BP 16 | ||
53 | #define HW_GPMI_COMPARE__MASK_BM 0xffff0000 | ||
54 | |||
55 | #define HW_GPMI_ECCCTRL (*(volatile uint32_t *)(HW_GPMI_BASE + 0x20)) | ||
56 | #define HW_GPMI_ECCCTRL__BUFFER_MASK_BP 0 | ||
57 | #define HW_GPMI_ECCCTRL__BUFFER_MASK_BM 0x1ff | ||
58 | #define HW_GPMI_ECCCTRL__ENABLE_ECC (1 << 12) | ||
59 | #define HW_GPMI_ECCCTRL__ECC_CMD_BP 13 | ||
60 | #define HW_GPMI_ECCCTRL__ECC_CMD_BM (0x3 << 13) | ||
61 | #define HW_GPMI_ECCCTRL__HANDLE_BP 16 | ||
62 | #define HW_GPMI_ECCCTRL__HANDLE_BM (0xffff << 16) | ||
63 | |||
64 | #define HW_GPMI_ECCCOUNT (*(volatile uint32_t *)(HW_GPMI_BASE + 0x30)) | ||
65 | #define HW_GPMI_ECCCOUNT__COUNT_BP 0 | ||
66 | #define HW_GPMI_ECCCOUNT__COUNT_BM 0xffff | ||
67 | |||
68 | #define HW_GPMI_PAYLOAD (*(volatile uint32_t *)(HW_GPMI_BASE + 0x40)) | ||
69 | |||
70 | #define HW_GPMI_AUXILIARY (*(volatile uint32_t *)(HW_GPMI_BASE + 0x50)) | ||
71 | |||
72 | #define HW_GPMI_CTRL1 (*(volatile uint32_t *)(HW_GPMI_BASE + 0x60)) | ||
73 | #define HW_GPMI_CTRL1__ATA_IRQRDY_POLARITY (1 << 2) | ||
74 | #define HW_GPMI_CTRL1__DEV_RESET (1 << 3) | ||
75 | #define HW_GPMI_CTRL1__ABORT_WAIT_FOR_READY(i) (1 << (4 + (i))) | ||
76 | #define HW_GPMI_CTRL1__BURST_EN (1 << 8) | ||
77 | #define HW_GPMI_CTRL1__TIMEOUT_IRQ (1 << 9) | ||
78 | #define HW_GPMI_CTRL1__RDN_DELAY_BP 12 | ||
79 | #define HW_GPMI_CTRL1__RDN_DELAY_BM (0xf << 12) | ||
80 | #define HW_GPMI_CTRL1__HALF_PERIOD (1 << 16) | ||
81 | #define HW_GPMI_CTRL1__DLL_ENABLE (1 << 17) | ||
82 | #define HW_GPMI_CTRL1__BCH_MODE (1 << 18) | ||
83 | #define HW_GPMI_CTRL1__GANGED_RDYBUSY (1 << 19) | ||
84 | #define HW_GPMI_CTRL1__CEx_SEL (1 << (20 + (x))) | ||
85 | |||
86 | #define HW_GPMI_TIMING0 (*(volatile uint32_t *)(HW_GPMI_BASE + 0x70)) | ||
87 | #define HW_GPMI_TIMING0__DATA_SETUP_BP 0 | ||
88 | #define HW_GPMI_TIMING0__DATA_SETUP_BM 0xff | ||
89 | #define HW_GPMI_TIMING0__DATA_HOLD_BP 8 | ||
90 | #define HW_GPMI_TIMING0__DATA_HOLD_BM 0xff00 | ||
91 | #define HW_GPMI_TIMING0__ADDRESS_SETUP_BP 16 | ||
92 | #define HW_GPMI_TIMING0__ADDRESS_SETUP_BM 0xff0000 | ||
93 | |||
94 | #define HW_GPMI_TIMING1 (*(volatile uint32_t *)(HW_GPMI_BASE + 0x80)) | ||
95 | #define HW_GPMI_TIMING1__DEVICE_BUSY_TIMEOUT_BP 16 | ||
96 | #define HW_GPMI_TIMING1__DEVICE_BUSY_TIMEOUT_BM 0xffff0000 | ||
97 | |||
98 | #define HW_GPMI_DATA (*(volatile uint32_t *)(HW_GPMI_BASE + 0xa0)) | ||
99 | |||
100 | #define HW_GPMI_STAT (*(volatile uint32_t *)(HW_GPMI_BASE + 0xb0)) | ||
101 | #define HW_GPMI_STAT__DEVx_ERROR(x) (1 << (x)) | ||
102 | #define HW_GPMI_STAT__FIFO_FULL (1 << 4) | ||
103 | #define HW_GPMI_STAT__FIFO_EMPTY (1 << 5) | ||
104 | #define HW_GPMI_STAT__INVALID_BUFFER_MASK (1 << 6) | ||
105 | #define HW_GPMI_STAT__RDY_TIMEOUT_BP 8 | ||
106 | #define HW_GPMI_STAT__RDY_TIMEOUT_BM (0xf << 8) | ||
107 | |||
108 | #define HW_GPMI_DEBUG (*(volatile uint32_t *)(HW_GPMI_BASE + 0xc0)) | ||
109 | |||
110 | #define HW_GPMI_VERSION (*(volatile uint32_t *)(HW_GPMI_BASE + 0xd0)) | ||
111 | |||
112 | #define HW_GPMI_DEBUG2 (*(volatile uint32_t *)(HW_GPMI_BASE + 0xe0)) | ||
113 | |||
114 | #define HW_GPMI_DEBUG3 (*(volatile uint32_t *)(HW_GPMI_BASE + 0xf0)) | ||
115 | |||
116 | /* ECC8 */ | ||
117 | |||
118 | #define HW_ECC8_BASE 0x80008000 | ||
119 | |||
120 | #define HW_ECC8_CTRL (*(volatile uint32_t *)(HW_ECC8_BASE + 0x0)) | ||
121 | #define HW_ECC8_CTRL__COMPLETE_IRQ (1 << 0) | ||
122 | #define HW_ECC8_CTRL__COMPLETE_IRQ_EN (1 << 8) | ||
123 | #define HW_ECC8_CTRL__THROTTLE_BP 24 | ||
124 | #define HW_ECC8_CTRL__THROTTLE_BM (0xf << 24) | ||
125 | #define HW_ECC8_CTRL__AHBM_SFTRST (1 << 29) | ||
126 | |||
127 | #define HW_ECC8_STATUS0 (*(volatile uint32_t *)(HW_ECC8_BASE + 0x10)) | ||
128 | #define HW_ECC8_STATUS0__UNCORRECTABLE (1 << 2) | ||
129 | #define HW_ECC8_STATUS0__CORRECTED (1 << 3) | ||
130 | #define HW_ECC8_STATUS0__ALLONES (1 << 4) | ||
131 | #define HW_ECC8_STATUS0__STATUS_AUX_BP 8 | ||
132 | #define HW_ECC8_STATUS0__STATUS_AUX_BM (0xf << 8) | ||
133 | #define HW_ECC8_STATUS0__COMPLETED_CE_BP 16 | ||
134 | #define HW_ECC8_STATUS0__COMPLETED_CE_BM (0xf << 16) | ||
135 | #define HW_ECC8_STATUS0__HANDLE_BP 20 | ||
136 | #define HW_ECC8_STATUS0__HANDLE_BM (0xfff << 20) | ||
137 | |||
138 | #define HW_ECC8_STATUS1 (*(volatile uint32_t *)(HW_ECC8_BASE + 0x20)) | ||
139 | #define HW_ECC8_STATUS1__STATUS_PAYLOADx_BP (4 * (x)) | ||
140 | #define HW_ECC8_STATUS1__STATUS_PAYLOADx_BM (0xf << (4 * (x))) | ||
141 | |||
142 | /* BCH */ | ||
143 | |||
144 | #define HW_BCH_BASE 0x8000a000 | ||
145 | |||
146 | #define HW_BCH_CTRL (*(volatile uint32_t *)(HW_BCH_BASE + 0x0)) | ||
147 | #define HW_BCH_CTRL__COMPLETE_IRQ (1 << 0) | ||
148 | #define HW_BCH_CTRL__COMPLETE_IRQ_EN (1 << 8) | ||
149 | #define HW_BCH_CTRL__M2M_ENABLE (1 << 16) | ||
150 | #define HW_BCH_CTRL__M2M_ENCODE (1 << 17) | ||
151 | #define HW_BCH_CTRL__M2M_LAYOUT_BP 18 | ||
152 | #define HW_BCH_CTRL__M2M_LAYOUT_BM (0x3 << 18) | ||
153 | |||
154 | #define HW_BCH_STATUS0 (*(volatile uint32_t *)(HW_BCH_BASE + 0x10)) | ||
155 | #define HW_BCH_STATUS0__UNCORRECTABLE (1 << 2) | ||
156 | #define HW_BCH_STATUS0__CORRECTED (1 << 3) | ||
157 | #define HW_BCH_STATUS0__ALLONES (1 << 4) | ||
158 | #define HW_BCH_STATUS0__STATUS_BLK0_BP 8 | ||
159 | #define HW_BCH_STATUS0__STATUS_BLK0_BM (0xf << 8) | ||
160 | #define HW_BCH_STATUS0__COMPLETED_CE_BP 16 | ||
161 | #define HW_BCH_STATUS0__COMPLETED_CE_BM (0xf << 16) | ||
162 | #define HW_BCH_STATUS0__HANDLE_BP 20 | ||
163 | #define HW_BCH_STATUS0__HANDLE_BM (0xfff << 20) | ||
164 | |||
165 | #define HW_BCH_MODE (*(volatile uint32_t *)(HW_BCH_BASE + 0x20)) | ||
166 | #define HW_BCH_MODE__ERASE_THRESHOLD_BP 0 | ||
167 | #define HW_BCH_MODE__ERASE_THRESHOLD_BM 0xff | ||
168 | |||
169 | #define HW_BCH_ENCODEPTR (*(volatile uint32_t *)(HW_BCH_BASE + 0x30)) | ||
170 | |||
171 | #define HW_BCH_DATAPTR (*(volatile uint32_t *)(HW_BCH_BASE + 0x40)) | ||
172 | |||
173 | #define HW_BCH_METAPTR (*(volatile uint32_t *)(HW_BCH_BASE + 0x50)) | ||
174 | |||
175 | #define HW_BCH_LAYOUTSELECT (*(volatile uint32_t *)(HW_BCH_BASE + 0x60)) | ||
176 | #define HW_BCH_LAYOUTSELECT__CSx_SELECT_BP(x) (2 * (x)) | ||
177 | #define HW_BCH_LAYOUTSELECT__CSx_SELECT_BM(x) (0x3 << (2 * (x))) | ||
178 | |||
179 | #define HW_BCH_FLASHxLAYOUT0(x) (*(volatile uint32_t *)(HW_BCH_BASE + 0x80 + (x) * 0x20)) | ||
180 | #define HW_BCH_FLASHxLAYOUT0__DATA0_SIZE_BP 0 | ||
181 | #define HW_BCH_FLASHxLAYOUT0__DATA0_SIZE_BM 0xfff | ||
182 | #define HW_BCH_FLASHxLAYOUT0__ECC0_BP 12 | ||
183 | #define HW_BCH_FLASHxLAYOUT0__ECC0_BM 0xf000 | ||
184 | #define HW_BCH_FLASHxLAYOUT0__META_SIZE_BP 16 | ||
185 | #define HW_BCH_FLASHxLAYOUT0__META_SIZE_BM 0xff0000 | ||
186 | #define HW_BCH_FLASHxLAYOUT0__NBLOCKS_BP 24 | ||
187 | #define HW_BCH_FLASHxLAYOUT0__NBLOCKS_BM 0xff000000 | ||
188 | |||
189 | #define HW_BCH_FLASHxLAYOUT1(x) (*(volatile uint32_t *)(HW_BCH_BASE + 0x90 + (x) * 0x20)) | ||
190 | #define HW_BCH_FLASHxLAYOUT1__DATAN_SIZE_BP 0 | ||
191 | #define HW_BCH_FLASHxLAYOUT1__DATAN_SIZE_BM 0xfff | ||
192 | #define HW_BCH_FLASHxLAYOUT1__ECCN_BP 12 | ||
193 | #define HW_BCH_FLASHxLAYOUT1__ECCN_BM 0xf000 | ||
194 | #define HW_BCH_FLASHxLAYOUT1__PAGE_SIZE_BP 16 | ||
195 | #define HW_BCH_FLASHxLAYOUT1__PAGE_SIZE_BM 0xffff0000 | ||
196 | |||
197 | #endif /* __GPMI_IMX233_H__ */ | ||