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author | Amaury Pouly <pamaury@rockbox.org> | 2011-06-30 17:31:40 +0000 |
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committer | Amaury Pouly <pamaury@rockbox.org> | 2011-06-30 17:31:40 +0000 |
commit | 617d1e9f6b7969aff5e45746b9c5e3cee9ce2c45 (patch) | |
tree | bf2015d298c2b6bc80189d09b73426380e08451f /firmware/target/arm/imx233/clkctrl-imx233.c | |
parent | 4a04c47a97517930b29f00b9d7f4d157cb69fa9b (diff) | |
download | rockbox-617d1e9f6b7969aff5e45746b9c5e3cee9ce2c45.tar.gz rockbox-617d1e9f6b7969aff5e45746b9c5e3cee9ce2c45.zip |
imx233/fuze+: ssp, dma, mmc now work properly, partially implement cpu frequency changing, implement panic waiting
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30104 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx233/clkctrl-imx233.c')
-rw-r--r-- | firmware/target/arm/imx233/clkctrl-imx233.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.c b/firmware/target/arm/imx233/clkctrl-imx233.c index 7701b84c41..ee77a77493 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.c +++ b/firmware/target/arm/imx233/clkctrl-imx233.c | |||
@@ -60,15 +60,25 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) | |||
60 | switch(clk) | 60 | switch(clk) |
61 | { | 61 | { |
62 | case CLK_PIX: | 62 | case CLK_PIX: |
63 | __REG_CLR(HW_CLKCTRL_PIX) = (1 << 12) - 1; | 63 | __REG_CLR(HW_CLKCTRL_PIX) = HW_CLKCTRL_PIX__DIV_BM; |
64 | __REG_SET(HW_CLKCTRL_PIX) = div; | 64 | __REG_SET(HW_CLKCTRL_PIX) = div; |
65 | while(HW_CLKCTRL_PIX & __CLK_BUSY); | 65 | while(HW_CLKCTRL_PIX & __CLK_BUSY); |
66 | break; | 66 | break; |
67 | case CLK_SSP: | 67 | case CLK_SSP: |
68 | __REG_CLR(HW_CLKCTRL_SSP) = (1 << 9) - 1; | 68 | __REG_CLR(HW_CLKCTRL_SSP) = HW_CLKCTRL_SSP__DIV_BM; |
69 | __REG_SET(HW_CLKCTRL_SSP) = div; | 69 | __REG_SET(HW_CLKCTRL_SSP) = div; |
70 | while(HW_CLKCTRL_SSP & __CLK_BUSY); | 70 | while(HW_CLKCTRL_SSP & __CLK_BUSY); |
71 | break; | 71 | break; |
72 | case CLK_CPU: | ||
73 | __REG_CLR(HW_CLKCTRL_CPU) = HW_CLKCTRL_CPU__DIV_CPU_BM; | ||
74 | __REG_SET(HW_CLKCTRL_CPU) = div; | ||
75 | while(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__BUSY_REF_CPU); | ||
76 | break; | ||
77 | case CLK_AHB: | ||
78 | __REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__DIV_BM; | ||
79 | __REG_SET(HW_CLKCTRL_HBUS) = div; | ||
80 | while(HW_CLKCTRL_HBUS & __CLK_BUSY); | ||
81 | break; | ||
72 | default: return; | 82 | default: return; |
73 | } | 83 | } |
74 | } | 84 | } |
@@ -81,6 +91,7 @@ void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) | |||
81 | { | 91 | { |
82 | case CLK_PIX: REG = &HW_CLKCTRL_FRAC_PIX; break; | 92 | case CLK_PIX: REG = &HW_CLKCTRL_FRAC_PIX; break; |
83 | case CLK_IO: REG = &HW_CLKCTRL_FRAC_IO; break; | 93 | case CLK_IO: REG = &HW_CLKCTRL_FRAC_IO; break; |
94 | case CLK_CPU: REG = &HW_CLKCTRL_FRAC_CPU; break; | ||
84 | default: return; | 95 | default: return; |
85 | } | 96 | } |
86 | 97 | ||
@@ -97,6 +108,7 @@ void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass) | |||
97 | { | 108 | { |
98 | case CLK_PIX: msk = HW_CLKCTRL_CLKSEQ__BYPASS_PIX; break; | 109 | case CLK_PIX: msk = HW_CLKCTRL_CLKSEQ__BYPASS_PIX; break; |
99 | case CLK_SSP: msk = HW_CLKCTRL_CLKSEQ__BYPASS_SSP; break; | 110 | case CLK_SSP: msk = HW_CLKCTRL_CLKSEQ__BYPASS_SSP; break; |
111 | case CLK_CPU: msk = HW_CLKCTRL_CLKSEQ__BYPASS_CPU; break; | ||
100 | default: return; | 112 | default: return; |
101 | } | 113 | } |
102 | 114 | ||