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author | Amaury Pouly <amaury.pouly@gmail.com> | 2012-05-19 13:16:17 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2012-05-19 16:10:51 +0200 |
commit | 553aeae9c63f789c969a954983e537244934903a (patch) | |
tree | 13a36bf8dc86d77b4ff5d7f6127b1df1c5c3e633 /firmware/target/arm/imx233/clkctrl-imx233.c | |
parent | 9022c69b646b43d7bd5ee2948f6abb9f51459aea (diff) | |
download | rockbox-553aeae9c63f789c969a954983e537244934903a.tar.gz rockbox-553aeae9c63f789c969a954983e537244934903a.zip |
imx233: fix clkctrl naming
Move to a more consistent naming convention like the other devices
Change-Id: I4ddbbee27ee9f5ae775c5776592ec7ce02b30948
Diffstat (limited to 'firmware/target/arm/imx233/clkctrl-imx233.c')
-rw-r--r-- | firmware/target/arm/imx233/clkctrl-imx233.c | 109 |
1 files changed, 55 insertions, 54 deletions
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.c b/firmware/target/arm/imx233/clkctrl-imx233.c index bfa707e3be..064ee8013b 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.c +++ b/firmware/target/arm/imx233/clkctrl-imx233.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #define __CLK_CLKGATE (1 << 31) | 23 | #define __CLK_CLKGATE (1 << 31) |
24 | #define __CLK_BUSY (1 << 29) | 24 | #define __CLK_BUSY (1 << 29) |
25 | 25 | ||
26 | void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable) | 26 | void imx233_clkctrl_enable_xtal(enum imx233_xtal_clk_t xtal_clk, bool enable) |
27 | { | 27 | { |
28 | if(enable) | 28 | if(enable) |
29 | __REG_CLR(HW_CLKCTRL_XTAL) = xtal_clk; | 29 | __REG_CLR(HW_CLKCTRL_XTAL) = xtal_clk; |
@@ -31,12 +31,12 @@ void imx233_enable_xtal_clock(enum imx233_xtal_clk_t xtal_clk, bool enable) | |||
31 | __REG_SET(HW_CLKCTRL_XTAL) = xtal_clk; | 31 | __REG_SET(HW_CLKCTRL_XTAL) = xtal_clk; |
32 | } | 32 | } |
33 | 33 | ||
34 | bool imx233_is_xtal_clock_enable(enum imx233_xtal_clk_t clk) | 34 | bool imx233_clkctrl_is_xtal_enable(enum imx233_xtal_clk_t clk) |
35 | { | 35 | { |
36 | return HW_CLKCTRL_XTAL & clk; | 36 | return HW_CLKCTRL_XTAL & clk; |
37 | } | 37 | } |
38 | 38 | ||
39 | void imx233_enable_clock(enum imx233_clock_t clk, bool enable) | 39 | void imx233_clkctrl_enable_clock(enum imx233_clock_t clk, bool enable) |
40 | { | 40 | { |
41 | volatile uint32_t *REG; | 41 | volatile uint32_t *REG; |
42 | switch(clk) | 42 | switch(clk) |
@@ -60,7 +60,7 @@ void imx233_enable_clock(enum imx233_clock_t clk, bool enable) | |||
60 | } | 60 | } |
61 | } | 61 | } |
62 | 62 | ||
63 | bool imx233_is_clock_enable(enum imx233_clock_t clk) | 63 | bool imx233_clkctrl_is_clock_enabled(enum imx233_clock_t clk) |
64 | { | 64 | { |
65 | volatile uint32_t *REG; | 65 | volatile uint32_t *REG; |
66 | switch(clk) | 66 | switch(clk) |
@@ -74,7 +74,7 @@ bool imx233_is_clock_enable(enum imx233_clock_t clk) | |||
74 | return !((*REG) & __CLK_CLKGATE); | 74 | return !((*REG) & __CLK_CLKGATE); |
75 | } | 75 | } |
76 | 76 | ||
77 | void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) | 77 | void imx233_clkctrl_set_clock_divisor(enum imx233_clock_t clk, int div) |
78 | { | 78 | { |
79 | /* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */ | 79 | /* warning: some registers like HW_CLKCTRL_PIX don't have a CLR/SET variant ! */ |
80 | switch(clk) | 80 | switch(clk) |
@@ -101,7 +101,7 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) | |||
101 | } | 101 | } |
102 | } | 102 | } |
103 | 103 | ||
104 | int imx233_get_clock_divisor(enum imx233_clock_t clk) | 104 | int imx233_clkctrl_get_clock_divisor(enum imx233_clock_t clk) |
105 | { | 105 | { |
106 | switch(clk) | 106 | switch(clk) |
107 | { | 107 | { |
@@ -119,7 +119,7 @@ int imx233_get_clock_divisor(enum imx233_clock_t clk) | |||
119 | } | 119 | } |
120 | } | 120 | } |
121 | 121 | ||
122 | void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) | 122 | void imx233_clkctrl_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) |
123 | { | 123 | { |
124 | /* NOTE: HW_CLKCTRL_FRAC only support byte access ! */ | 124 | /* NOTE: HW_CLKCTRL_FRAC only support byte access ! */ |
125 | volatile uint8_t *REG; | 125 | volatile uint8_t *REG; |
@@ -142,7 +142,7 @@ void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) | |||
142 | *REG = HW_CLKCTRL_FRAC_XX__CLKGATEXX;; | 142 | *REG = HW_CLKCTRL_FRAC_XX__CLKGATEXX;; |
143 | } | 143 | } |
144 | 144 | ||
145 | int imx233_get_fractional_divisor(enum imx233_clock_t clk) | 145 | int imx233_clkctrl_get_fractional_divisor(enum imx233_clock_t clk) |
146 | { | 146 | { |
147 | /* NOTE: HW_CLKCTRL_FRAC only support byte access ! */ | 147 | /* NOTE: HW_CLKCTRL_FRAC only support byte access ! */ |
148 | volatile uint8_t *REG; | 148 | volatile uint8_t *REG; |
@@ -166,7 +166,7 @@ int imx233_get_fractional_divisor(enum imx233_clock_t clk) | |||
166 | return *REG & ~HW_CLKCTRL_FRAC_XX__XX_STABLE; | 166 | return *REG & ~HW_CLKCTRL_FRAC_XX__XX_STABLE; |
167 | } | 167 | } |
168 | 168 | ||
169 | void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass) | 169 | void imx233_clkctrl_set_bypass_pll(enum imx233_clock_t clk, bool bypass) |
170 | { | 170 | { |
171 | uint32_t msk; | 171 | uint32_t msk; |
172 | switch(clk) | 172 | switch(clk) |
@@ -184,7 +184,7 @@ void imx233_set_bypass_pll(enum imx233_clock_t clk, bool bypass) | |||
184 | __REG_CLR(HW_CLKCTRL_CLKSEQ) = msk; | 184 | __REG_CLR(HW_CLKCTRL_CLKSEQ) = msk; |
185 | } | 185 | } |
186 | 186 | ||
187 | bool imx233_get_bypass_pll(enum imx233_clock_t clk) | 187 | bool imx233_clkctrl_get_bypass_pll(enum imx233_clock_t clk) |
188 | { | 188 | { |
189 | uint32_t msk; | 189 | uint32_t msk; |
190 | switch(clk) | 190 | switch(clk) |
@@ -199,7 +199,7 @@ bool imx233_get_bypass_pll(enum imx233_clock_t clk) | |||
199 | return HW_CLKCTRL_CLKSEQ & msk; | 199 | return HW_CLKCTRL_CLKSEQ & msk; |
200 | } | 200 | } |
201 | 201 | ||
202 | void imx233_enable_usb_pll(bool enable) | 202 | void imx233_clkctrl_enable_usb_pll(bool enable) |
203 | { | 203 | { |
204 | if(enable) | 204 | if(enable) |
205 | __REG_SET(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS; | 205 | __REG_SET(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS; |
@@ -207,23 +207,23 @@ void imx233_enable_usb_pll(bool enable) | |||
207 | __REG_CLR(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS; | 207 | __REG_CLR(HW_CLKCTRL_PLLCTRL0) = HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS; |
208 | } | 208 | } |
209 | 209 | ||
210 | bool imx233_is_usb_pll_enable(void) | 210 | bool imx233_clkctrl_is_usb_pll_enabled(void) |
211 | { | 211 | { |
212 | return HW_CLKCTRL_PLLCTRL0 & HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS; | 212 | return HW_CLKCTRL_PLLCTRL0 & HW_CLKCTRL_PLLCTRL0__EN_USB_CLKS; |
213 | } | 213 | } |
214 | 214 | ||
215 | void imx233_set_auto_slow_divisor(enum imx233_as_div_t div) | 215 | void imx233_clkctrl_set_auto_slow_divisor(enum imx233_as_div_t div) |
216 | { | 216 | { |
217 | __REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__SLOW_DIV_BM; | 217 | __REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__SLOW_DIV_BM; |
218 | __REG_SET(HW_CLKCTRL_HBUS) = div; | 218 | __REG_SET(HW_CLKCTRL_HBUS) = div; |
219 | } | 219 | } |
220 | 220 | ||
221 | enum imx233_as_div_t imx233_get_auto_slow_divisor(void) | 221 | enum imx233_as_div_t imx233_clkctrl_get_auto_slow_divisor(void) |
222 | { | 222 | { |
223 | return __XTRACT(HW_CLKCTRL_HBUS, SLOW_DIV); | 223 | return __XTRACT(HW_CLKCTRL_HBUS, SLOW_DIV); |
224 | } | 224 | } |
225 | 225 | ||
226 | void imx233_enable_auto_slow(bool enable) | 226 | void imx233_clkctrl_enable_auto_slow(bool enable) |
227 | { | 227 | { |
228 | if(enable) | 228 | if(enable) |
229 | __REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE; | 229 | __REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE; |
@@ -231,12 +231,12 @@ void imx233_enable_auto_slow(bool enable) | |||
231 | __REG_SET(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE; | 231 | __REG_SET(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__AUTO_SLOW_MODE; |
232 | } | 232 | } |
233 | 233 | ||
234 | bool imx233_is_auto_slow_enable(void) | 234 | bool imx233_clkctrl_is_auto_slow_enabled(void) |
235 | { | 235 | { |
236 | return HW_CLKCTRL_HBUS & HW_CLKCTRL_HBUS__AUTO_SLOW_MODE; | 236 | return HW_CLKCTRL_HBUS & HW_CLKCTRL_HBUS__AUTO_SLOW_MODE; |
237 | } | 237 | } |
238 | 238 | ||
239 | void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable) | 239 | void imx233_clkctrl_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enable) |
240 | { | 240 | { |
241 | if(enable) | 241 | if(enable) |
242 | __REG_SET(HW_CLKCTRL_HBUS) = monitor; | 242 | __REG_SET(HW_CLKCTRL_HBUS) = monitor; |
@@ -244,17 +244,17 @@ void imx233_enable_auto_slow_monitor(enum imx233_as_monitor_t monitor, bool enab | |||
244 | __REG_CLR(HW_CLKCTRL_HBUS) = monitor; | 244 | __REG_CLR(HW_CLKCTRL_HBUS) = monitor; |
245 | } | 245 | } |
246 | 246 | ||
247 | bool imx233_is_auto_slow_monitor_enable(enum imx233_as_monitor_t monitor) | 247 | bool imx233_clkctrl_is_auto_slow_monitor_enabled(enum imx233_as_monitor_t monitor) |
248 | { | 248 | { |
249 | return HW_CLKCTRL_HBUS & monitor; | 249 | return HW_CLKCTRL_HBUS & monitor; |
250 | } | 250 | } |
251 | 251 | ||
252 | unsigned imx233_get_clock_freq(enum imx233_clock_t clk) | 252 | unsigned imx233_clkctrl_get_clock_freq(enum imx233_clock_t clk) |
253 | { | 253 | { |
254 | switch(clk) | 254 | switch(clk) |
255 | { | 255 | { |
256 | case CLK_PLL: /* PLL: 480MHz when enable */ | 256 | case CLK_PLL: /* PLL: 480MHz when enable */ |
257 | return imx233_is_clock_enable(CLK_PLL) ? 480000 : 0; | 257 | return imx233_clkctrl_is_clock_enabled(CLK_PLL) ? 480000 : 0; |
258 | case CLK_XTAL: /* crystal: 24MHz */ | 258 | case CLK_XTAL: /* crystal: 24MHz */ |
259 | return 24000; | 259 | return 24000; |
260 | case CLK_CPU: | 260 | case CLK_CPU: |
@@ -263,78 +263,78 @@ unsigned imx233_get_clock_freq(enum imx233_clock_t clk) | |||
263 | /* In bypass mode: clk_p derived from clk_xtal via int/binfrac divider | 263 | /* In bypass mode: clk_p derived from clk_xtal via int/binfrac divider |
264 | * otherwise, clk_p derived from clk_cpu via int div and clk_cpu | 264 | * otherwise, clk_p derived from clk_cpu via int div and clk_cpu |
265 | * derived from clk_pll fracdiv */ | 265 | * derived from clk_pll fracdiv */ |
266 | if(imx233_get_bypass_pll(CLK_CPU)) | 266 | if(imx233_clkctrl_get_bypass_pll(CLK_CPU)) |
267 | { | 267 | { |
268 | ref = imx233_get_clock_freq(CLK_XTAL); | 268 | ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); |
269 | /* Integer divide mode vs fractional divide mode */ | 269 | /* Integer divide mode vs fractional divide mode */ |
270 | if(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__DIV_XTAL_FRAC_EN) | 270 | if(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__DIV_XTAL_FRAC_EN) |
271 | 271 | ||
272 | return (ref * __XTRACT(HW_CLKCTRL_CPU, DIV_XTAL)) / 32; | 272 | return (ref * __XTRACT(HW_CLKCTRL_CPU, DIV_XTAL)) / 32; |
273 | else | 273 | else |
274 | return ref / imx233_get_clock_divisor(CLK_CPU); | 274 | return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU); |
275 | } | 275 | } |
276 | else | 276 | else |
277 | { | 277 | { |
278 | ref = imx233_get_clock_freq(CLK_PLL); | 278 | ref = imx233_clkctrl_get_clock_freq(CLK_PLL); |
279 | /* fractional divider enable ? */ | 279 | /* fractional divider enable ? */ |
280 | if(imx233_get_fractional_divisor(CLK_CPU) != 0) | 280 | if(imx233_clkctrl_get_fractional_divisor(CLK_CPU) != 0) |
281 | ref = (ref * 18) / imx233_get_fractional_divisor(CLK_CPU); | 281 | ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_CPU); |
282 | return ref / imx233_get_clock_divisor(CLK_CPU); | 282 | return ref / imx233_clkctrl_get_clock_divisor(CLK_CPU); |
283 | } | 283 | } |
284 | } | 284 | } |
285 | case CLK_HBUS: | 285 | case CLK_HBUS: |
286 | { | 286 | { |
287 | /* Derived from clk_p via integer/fractional div */ | 287 | /* Derived from clk_p via integer/fractional div */ |
288 | unsigned ref = imx233_get_clock_freq(CLK_CPU); | 288 | unsigned ref = imx233_clkctrl_get_clock_freq(CLK_CPU); |
289 | if(imx233_get_fractional_divisor(CLK_HBUS) != 0) | 289 | if(imx233_clkctrl_get_fractional_divisor(CLK_HBUS) != 0) |
290 | ref = (ref * imx233_get_fractional_divisor(CLK_HBUS)) / 32; | 290 | ref = (ref * imx233_clkctrl_get_fractional_divisor(CLK_HBUS)) / 32; |
291 | if(imx233_get_clock_divisor(CLK_HBUS) != 0) | 291 | if(imx233_clkctrl_get_clock_divisor(CLK_HBUS) != 0) |
292 | ref /= imx233_get_clock_divisor(CLK_HBUS); | 292 | ref /= imx233_clkctrl_get_clock_divisor(CLK_HBUS); |
293 | return ref; | 293 | return ref; |
294 | } | 294 | } |
295 | case CLK_IO: | 295 | case CLK_IO: |
296 | { | 296 | { |
297 | /* Derived from clk_pll via fracdiv */ | 297 | /* Derived from clk_pll via fracdiv */ |
298 | unsigned ref = imx233_get_clock_freq(CLK_PLL); | 298 | unsigned ref = imx233_clkctrl_get_clock_freq(CLK_PLL); |
299 | if(imx233_get_fractional_divisor(CLK_IO) != 0) | 299 | if(imx233_clkctrl_get_fractional_divisor(CLK_IO) != 0) |
300 | ref = (ref * 18) / imx233_get_fractional_divisor(CLK_IO); | 300 | ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_IO); |
301 | return ref; | 301 | return ref; |
302 | } | 302 | } |
303 | case CLK_PIX: | 303 | case CLK_PIX: |
304 | { | 304 | { |
305 | unsigned ref; | 305 | unsigned ref; |
306 | /* Derived from clk_pll or clk_xtal */ | 306 | /* Derived from clk_pll or clk_xtal */ |
307 | if(!imx233_is_clock_enable(CLK_PIX)) | 307 | if(!imx233_clkctrl_is_clock_enabled(CLK_PIX)) |
308 | ref = 0; | 308 | ref = 0; |
309 | else if(imx233_get_bypass_pll(CLK_PIX)) | 309 | else if(imx233_clkctrl_get_bypass_pll(CLK_PIX)) |
310 | ref = imx233_get_clock_freq(CLK_XTAL); | 310 | ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); |
311 | else | 311 | else |
312 | { | 312 | { |
313 | ref = imx233_get_clock_freq(CLK_PLL); | 313 | ref = imx233_clkctrl_get_clock_freq(CLK_PLL); |
314 | if(imx233_get_fractional_divisor(CLK_PIX) != 0) | 314 | if(imx233_clkctrl_get_fractional_divisor(CLK_PIX) != 0) |
315 | ref = (ref * 18) / imx233_get_fractional_divisor(CLK_PIX); | 315 | ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_PIX); |
316 | } | 316 | } |
317 | return ref / imx233_get_clock_divisor(CLK_PIX); | 317 | return ref / imx233_clkctrl_get_clock_divisor(CLK_PIX); |
318 | } | 318 | } |
319 | case CLK_SSP: | 319 | case CLK_SSP: |
320 | { | 320 | { |
321 | unsigned ref; | 321 | unsigned ref; |
322 | /* Derived from clk_pll or clk_xtal */ | 322 | /* Derived from clk_pll or clk_xtal */ |
323 | if(!imx233_is_clock_enable(CLK_SSP)) | 323 | if(!imx233_clkctrl_is_clock_enabled(CLK_SSP)) |
324 | ref = 0; | 324 | ref = 0; |
325 | else if(imx233_get_bypass_pll(CLK_SSP)) | 325 | else if(imx233_clkctrl_get_bypass_pll(CLK_SSP)) |
326 | ref = imx233_get_clock_freq(CLK_XTAL); | 326 | ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); |
327 | else | 327 | else |
328 | ref = imx233_get_clock_freq(CLK_IO); | 328 | ref = imx233_clkctrl_get_clock_freq(CLK_IO); |
329 | return ref / imx233_get_clock_divisor(CLK_SSP); | 329 | return ref / imx233_clkctrl_get_clock_divisor(CLK_SSP); |
330 | } | 330 | } |
331 | case CLK_EMI: | 331 | case CLK_EMI: |
332 | { | 332 | { |
333 | unsigned ref; | 333 | unsigned ref; |
334 | /* Derived from clk_pll or clk_xtal */ | 334 | /* Derived from clk_pll or clk_xtal */ |
335 | if(imx233_get_bypass_pll(CLK_EMI)) | 335 | if(imx233_clkctrl_get_bypass_pll(CLK_EMI)) |
336 | { | 336 | { |
337 | ref = imx233_get_clock_freq(CLK_XTAL); | 337 | ref = imx233_clkctrl_get_clock_freq(CLK_XTAL); |
338 | if(HW_CLKCTRL_EMI & HW_CLKCTRL_EMI__CLKGATE) | 338 | if(HW_CLKCTRL_EMI & HW_CLKCTRL_EMI__CLKGATE) |
339 | return 0; | 339 | return 0; |
340 | else | 340 | else |
@@ -342,14 +342,15 @@ unsigned imx233_get_clock_freq(enum imx233_clock_t clk) | |||
342 | } | 342 | } |
343 | else | 343 | else |
344 | { | 344 | { |
345 | ref = imx233_get_clock_freq(CLK_PLL); | 345 | ref = imx233_clkctrl_get_clock_freq(CLK_PLL); |
346 | if(imx233_get_fractional_divisor(CLK_EMI) != 0) | 346 | if(imx233_clkctrl_get_fractional_divisor(CLK_EMI) != 0) |
347 | ref = (ref * 18) / imx233_get_fractional_divisor(CLK_EMI); | 347 | ref = (ref * 18) / imx233_clkctrl_get_fractional_divisor(CLK_EMI); |
348 | return ref / imx233_get_clock_divisor(CLK_EMI); | 348 | return ref / imx233_clkctrl_get_clock_divisor(CLK_EMI); |
349 | } | 349 | } |
350 | } | 350 | } |
351 | case CLK_XBUS: | 351 | case CLK_XBUS: |
352 | return imx233_get_clock_freq(CLK_XTAL) / imx233_get_clock_divisor(CLK_XBUS); | 352 | return imx233_clkctrl_get_clock_freq(CLK_XTAL) / |
353 | imx233_clkctrl_get_clock_divisor(CLK_XBUS); | ||
353 | default: | 354 | default: |
354 | return 0; | 355 | return 0; |
355 | } | 356 | } |