summaryrefslogtreecommitdiff
path: root/firmware/target/arm/i2s-pp.c
diff options
context:
space:
mode:
authorMichael Sevakis <jethead71@rockbox.org>2010-06-26 10:07:17 +0000
committerMichael Sevakis <jethead71@rockbox.org>2010-06-26 10:07:17 +0000
commitb15a523870d6aa45b38b92547053beb986b92d9a (patch)
tree8b75fe5f13a3418186cb11c01062ad415490036b /firmware/target/arm/i2s-pp.c
parentac622c6d673c708d48527db8a189401422a5d03c (diff)
downloadrockbox-b15a523870d6aa45b38b92547053beb986b92d9a.tar.gz
rockbox-b15a523870d6aa45b38b92547053beb986b92d9a.zip
e200v1/c200v1: Implement limited samplerate switching. Rates 24kHz and below are being a bear as far as minor crackling at higher amplitude-- leave them out for the time being since no solution is currently evident. 48, 44, 32 (rec rates 24, 22, 16) seem perfectly fine. I'm betting c200 is ok to include because it uses the same setup as e200.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27139 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/i2s-pp.c')
-rw-r--r--firmware/target/arm/i2s-pp.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/firmware/target/arm/i2s-pp.c b/firmware/target/arm/i2s-pp.c
index c9d66d53ae..83f39515c4 100644
--- a/firmware/target/arm/i2s-pp.c
+++ b/firmware/target/arm/i2s-pp.c
@@ -28,6 +28,10 @@
28#include "system.h" 28#include "system.h"
29#include "cpu.h" 29#include "cpu.h"
30#include "i2s.h" 30#include "i2s.h"
31#if defined (SANSA_E200) || defined (SANSA_C200)
32#include "audiohw.h"
33#include "pcm_sampr.h"
34#endif
31 35
32#if CONFIG_CPU == PP5002 36#if CONFIG_CPU == PP5002
33void i2s_reset(void) 37void i2s_reset(void)
@@ -70,6 +74,8 @@ void i2s_reset(void)
70 IISCLK = (IISCLK & ~0x1ff) | 31; 74 IISCLK = (IISCLK & ~0x1ff) | 31;
71 IISDIV = (IISDIV & ~0xc0000000) | (2 << 30); 75 IISDIV = (IISDIV & ~0xc0000000) | (2 << 30);
72 IISDIV = (IISDIV & ~0x3f) | 16; 76 IISDIV = (IISDIV & ~0x3f) | 16;
77#elif defined (SANSA_E200) || defined (SANSA_C200)
78 audiohw_set_sampr_dividers(HW_FREQ_DEFAULT);
73#else 79#else
74 IISCLK = (IISCLK & ~0x1ff) | 33; 80 IISCLK = (IISCLK & ~0x1ff) | 33;
75 IISDIV = 7; 81 IISDIV = 7;