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author | Greg White <gwhite@rockbox.org> | 2007-01-05 04:17:25 +0000 |
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committer | Greg White <gwhite@rockbox.org> | 2007-01-05 04:17:25 +0000 |
commit | 5668505d6b9515c21488e7be1ea40f076d0eb14e (patch) | |
tree | c01e1eba11cc26ac2d2593c86b4fe68edaad759a /firmware/target/arm/gigabeat/meg-fx | |
parent | a11f1eac1ce69c53fe316ac0de4197e9c7cde143 (diff) | |
download | rockbox-5668505d6b9515c21488e7be1ea40f076d0eb14e.tar.gz rockbox-5668505d6b9515c21488e7be1ea40f076d0eb14e.zip |
Switch DMA wait loop to idle CPU
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11914 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/gigabeat/meg-fx')
-rw-r--r-- | firmware/target/arm/gigabeat/meg-fx/ata-meg-fx.c | 29 | ||||
-rw-r--r-- | firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c | 2 |
2 files changed, 20 insertions, 11 deletions
diff --git a/firmware/target/arm/gigabeat/meg-fx/ata-meg-fx.c b/firmware/target/arm/gigabeat/meg-fx/ata-meg-fx.c index de4626e288..361b9d4b6f 100644 --- a/firmware/target/arm/gigabeat/meg-fx/ata-meg-fx.c +++ b/firmware/target/arm/gigabeat/meg-fx/ata-meg-fx.c | |||
@@ -57,14 +57,15 @@ void copy_read_sectors(unsigned char* buf, int wordcount) | |||
57 | /* This should never happen, but worth watching for */ | 57 | /* This should never happen, but worth watching for */ |
58 | if(wordcount > (1 << 18)) | 58 | if(wordcount > (1 << 18)) |
59 | panicf("atd-meg-fx.c: copy_read_sectors: too many sectors per read!"); | 59 | panicf("atd-meg-fx.c: copy_read_sectors: too many sectors per read!"); |
60 | #undef GIGABEAT_DEBUG_ATA | 60 | |
61 | //#define GIGABEAT_DEBUG_ATA | ||
61 | #ifdef GIGABEAT_DEBUG_ATA | 62 | #ifdef GIGABEAT_DEBUG_ATA |
62 | static int line = 0; | 63 | static int line = 0; |
63 | static char str[256]; | 64 | static char str[256]; |
64 | snprintf(str, sizeof(str), "DMA to %08x, %d", buf, wordcount); | 65 | snprintf(str, sizeof(str), "ODD DMA to %08x, %d", buf, wordcount); |
65 | lcd_puts(16, line, str); | 66 | lcd_puts(10, line, str); |
66 | line = (line+1) % 32; | 67 | line = (line+1) % 32; |
67 | lcd_update(); | 68 | lcd_update(); |
68 | #endif | 69 | #endif |
69 | /* Reset the channel */ | 70 | /* Reset the channel */ |
70 | DMASKTRIG0 |= 4; | 71 | DMASKTRIG0 |= 4; |
@@ -81,20 +82,26 @@ void copy_read_sectors(unsigned char* buf, int wordcount) | |||
81 | DIDSTC0 = 0; | 82 | DIDSTC0 = 0; |
82 | 83 | ||
83 | /* DACK/DREQ Sync to AHB, Int on Transfer complete, Whole service, No reload, 16-bit transfers */ | 84 | /* DACK/DREQ Sync to AHB, Int on Transfer complete, Whole service, No reload, 16-bit transfers */ |
84 | DCON0 = ((1 << 30) | (1<<27) | (1<<22) | (1<<20)) | wordcount; | 85 | DCON0 = ((1 << 30) | (1<< 29) | (1<<27) | (1<<22) | (1<<20)) | wordcount; |
85 | 86 | ||
86 | /* Activate the channel */ | 87 | /* Activate the channel */ |
87 | DMASKTRIG0 = 0x2; | 88 | DMASKTRIG0 = 0x2; |
88 | 89 | ||
89 | /* Dump cache for the buffer */ | 90 | invalidate_dcache_range((void *)buf, wordcount*2); |
90 | dump_dcache_range((void *)buf, wordcount*2); | ||
91 | 91 | ||
92 | INTMSK &= ~(1<<17); /* unmask the interrupt */ | ||
93 | SRCPND = (1<<17); /* clear any pending interrupts */ | ||
92 | /* Start DMA */ | 94 | /* Start DMA */ |
93 | DMASKTRIG0 |= 0x1; | 95 | DMASKTRIG0 |= 0x1; |
94 | 96 | ||
95 | /* Wait for transfer to complete */ | 97 | /* Wait for transfer to complete */ |
96 | while((DSTAT0 & 0x000fffff)) | 98 | while((DSTAT0 & 0x000fffff)) |
97 | yield(); | 99 | CLKCON |= (1 << 2); /* set IDLE bit */ |
100 | /* Dump cache for the buffer */ | ||
101 | } | ||
102 | |||
103 | void dma0(void) | ||
104 | { | ||
98 | } | 105 | } |
99 | 106 | ||
100 | 107 | ||
diff --git a/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c b/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c index b8bcda3c95..b2b4a6207b 100644 --- a/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c +++ b/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c | |||
@@ -33,6 +33,8 @@ void irq(void) | |||
33 | /* Timer 4 */ | 33 | /* Timer 4 */ |
34 | if ((intpending & TIMER4_MASK) != 0) | 34 | if ((intpending & TIMER4_MASK) != 0) |
35 | timer4(); | 35 | timer4(); |
36 | else if ((intpending & DMA0_MASK) != 0) | ||
37 | dma0(); | ||
36 | else | 38 | else |
37 | { | 39 | { |
38 | /* unexpected interrupt */ | 40 | /* unexpected interrupt */ |