diff options
author | Amaury Pouly <pamaury@rockbox.org> | 2010-06-21 20:25:31 +0000 |
---|---|---|
committer | Amaury Pouly <pamaury@rockbox.org> | 2010-06-21 20:25:31 +0000 |
commit | 7d46f4e251835077e98a432a3045fd4a3506134d (patch) | |
tree | 1be98e2fce2834b47d469cba4cd0ef08cb9d6e49 /firmware/target/arm/as3525 | |
parent | f86ee556cf003744ee209a0c63c73804b012b153 (diff) | |
download | rockbox-7d46f4e251835077e98a432a3045fd4a3506134d.tar.gz rockbox-7d46f4e251835077e98a432a3045fd4a3506134d.zip |
as3525v2-usb: add a few missing define for completeness, finish reorganization of the header
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27030 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/as3525')
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.h | 50 |
1 files changed, 24 insertions, 26 deletions
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.h b/firmware/target/arm/as3525/usb-drv-as3525v2.h index 07b4f518fa..0cd58a1544 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.h +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.h | |||
@@ -59,6 +59,7 @@ | |||
59 | #define GAHBCFG BASE_REG(0x008) | 59 | #define GAHBCFG BASE_REG(0x008) |
60 | #define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */ | 60 | #define GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */ |
61 | #define GAHBCFG_hburstlen_bitp 1 | 61 | #define GAHBCFG_hburstlen_bitp 1 |
62 | #define GAHBCFG_hburstlen_bits 0xf | ||
62 | #define GAHBCFG_INT_DMA_BURST_SINGLE 0 | 63 | #define GAHBCFG_INT_DMA_BURST_SINGLE 0 |
63 | #define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ | 64 | #define GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */ |
64 | #define GAHBCFG_INT_DMA_BURST_INCR4 3 | 65 | #define GAHBCFG_INT_DMA_BURST_INCR4 3 |
@@ -248,7 +249,6 @@ | |||
248 | #define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ | 249 | #define DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */ |
249 | #define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ | 250 | #define DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */ |
250 | #define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ | 251 | #define DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */ |
251 | /* "documented" in constants.h only */ | ||
252 | #define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ | 252 | #define DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */ |
253 | 253 | ||
254 | /** Device Status Register */ | 254 | /** Device Status Register */ |
@@ -261,7 +261,7 @@ | |||
261 | #define DSTS_ENUMSPD_LS_PHY_6MHZ 2 | 261 | #define DSTS_ENUMSPD_LS_PHY_6MHZ 2 |
262 | #define DSTS_ENUMSPD_FS_PHY_48MHZ 3 | 262 | #define DSTS_ENUMSPD_FS_PHY_48MHZ 3 |
263 | #define DSTS_errticerr (1 << 3) /** Erratic errors ? */ | 263 | #define DSTS_errticerr (1 << 3) /** Erratic errors ? */ |
264 | #define DSTS_soffn_bitp 7 /** Frame or Microframe Number of the received SOF */ | 264 | #define DSTS_soffn_bitp 8 /** Frame or Microframe Number of the received SOF */ |
265 | #define DSTS_soffn_bits 0x3fff | 265 | #define DSTS_soffn_bits 0x3fff |
266 | 266 | ||
267 | /** Device IN Endpoint Common Interrupt Mask Register */ | 267 | /** Device IN Endpoint Common Interrupt Mask Register */ |
@@ -330,33 +330,12 @@ | |||
330 | /** Device IN EPs empty Inr. Mask Register */ | 330 | /** Device IN EPs empty Inr. Mask Register */ |
331 | #define FFEMPTYMSK DEV_REG(0x34) | 331 | #define FFEMPTYMSK DEV_REG(0x34) |
332 | 332 | ||
333 | #define PCGCCTL BASE_REG(0xE00) /** Power and Clock Gating Control Register */ | ||
333 | 334 | ||
334 | /* 0<=ep<=15, you can use ep=0 */ | ||
335 | /** Device IN Endpoint (ep) Control Register */ | 335 | /** Device IN Endpoint (ep) Control Register */ |
336 | #define DIEPCTL(ep) DEV_REG(0x100 + (ep) * 0x20) | 336 | #define DIEPCTL(ep) DEV_REG(0x100 + (ep) * 0x20) |
337 | /** Device IN Endpoint (ep) Interrupt Register */ | ||
338 | #define DIEPINT(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x8) | ||
339 | /** Device IN Endpoint (ep) Transfer Size Register */ | ||
340 | #define DIEPTSIZ(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x10) | ||
341 | /** Device IN Endpoint (ep) DMA Address Register */ | ||
342 | #define DIEPDMA(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x14) | ||
343 | /** Device IN Endpoint (ep) Transmit FIFO Status Register */ | ||
344 | #define DTXFSTS(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x18) | ||
345 | |||
346 | /* 0<=ep<=15, you can use ep=0 */ | ||
347 | /** Device OUT Endpoint (ep) Control Register */ | 337 | /** Device OUT Endpoint (ep) Control Register */ |
348 | #define DOEPCTL(ep) DEV_REG(0x300 + (ep) * 0x20) | 338 | #define DOEPCTL(ep) DEV_REG(0x300 + (ep) * 0x20) |
349 | /** Device OUT Endpoint (ep) Frame number Register */ | ||
350 | #define DOEPFN(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x4) | ||
351 | /** Device Endpoint (ep) Interrupt Register */ | ||
352 | #define DOEPINT(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x8) | ||
353 | /** Device OUT Endpoint (ep) Transfer Size Register */ | ||
354 | #define DOEPTSIZ(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x10) | ||
355 | /** Device Endpoint (ep) DMA Address Register */ | ||
356 | #define DOEPDMA(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x14) | ||
357 | |||
358 | #define PCGCCTL BASE_REG(0xE00) /** Power and Clock Gating Control Register */ | ||
359 | |||
360 | 339 | ||
361 | /** Maximum Packet Size | 340 | /** Maximum Packet Size |
362 | * IN/OUT EPn | 341 | * IN/OUT EPn |
@@ -433,6 +412,10 @@ | |||
433 | #define DEPCTL_epdis (1 << 30) /** Endpoint disable */ | 412 | #define DEPCTL_epdis (1 << 30) /** Endpoint disable */ |
434 | #define DEPCTL_epena (1 << 31) /** Endpoint enable */ | 413 | #define DEPCTL_epena (1 << 31) /** Endpoint enable */ |
435 | 414 | ||
415 | /** Device IN Endpoint (ep) Transfer Size Register */ | ||
416 | #define DIEPTSIZ(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x10) | ||
417 | /** Device OUT Endpoint (ep) Transfer Size Register */ | ||
418 | #define DOEPTSIZ(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x10) | ||
436 | 419 | ||
437 | /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ | 420 | /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */ |
438 | #define DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */ | 421 | #define DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */ |
@@ -442,12 +425,27 @@ | |||
442 | #define DEPTSIZ_mc_bits 0x3 | 425 | #define DEPTSIZ_mc_bits 0x3 |
443 | 426 | ||
444 | /* idem but for i=0 */ | 427 | /* idem but for i=0 */ |
445 | #define DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */ | 428 | #define DEPTSIZ0_xfersize_bitp 0 /** Transfer Size */ |
429 | #define DEPTSIZ0_xfersize_bits 0x7f | ||
446 | #define DEPTSIZ0_pkcnt_bitp 19 /** Packet Count */ | 430 | #define DEPTSIZ0_pkcnt_bitp 19 /** Packet Count */ |
447 | #define DEPTSIZ0_pkcnt_bits 0x1 | 431 | #define DEPTSIZ0_pkcnt_bits 0x3 |
448 | #define DEPTSIZ0_supcnt_bitp 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ | 432 | #define DEPTSIZ0_supcnt_bitp 29 /** Setup Packet Count (DOEPTSIZ0 Only) */ |
449 | #define DEPTSIZ0_supcnt_bits 0x3 | 433 | #define DEPTSIZ0_supcnt_bits 0x3 |
450 | 434 | ||
435 | /** Device IN Endpoint (ep) Interrupt Register */ | ||
436 | #define DIEPINT(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x8) | ||
437 | /** Device IN Endpoint (ep) DMA Address Register */ | ||
438 | #define DIEPDMA(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x14) | ||
439 | /** Device IN Endpoint (ep) Transmit FIFO Status Register */ | ||
440 | #define DTXFSTS(ep) DEV_REG(0x100 + (ep) * 0x20 + 0x18) | ||
441 | |||
442 | /** Device OUT Endpoint (ep) Frame number Register */ | ||
443 | #define DOEPFN(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x4) | ||
444 | /** Device Endpoint (ep) Interrupt Register */ | ||
445 | #define DOEPINT(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x8) | ||
446 | /** Device Endpoint (ep) DMA Address Register */ | ||
447 | #define DOEPDMA(ep) DEV_REG(0x300 + (ep) * 0x20 + 0x14) | ||
448 | |||
451 | /** | 449 | /** |
452 | * Parameters | 450 | * Parameters |
453 | */ | 451 | */ |